With the increase of transistors' density, popularity of System on Chip (SoC) has increased exponentially. As a communication module for SoC, Network on Chip (NoC) framework has been adapted as its backbone. In this paper, we propose a methodology for designing area-optimized application specific NoC while providing hard Quality of Service (QoS) guarantees for real time flows. The novelty of th...

We introduce two properties of the design process called the arbitrary composability and the linear effort properties. We argue that a design paradigm, which has these two properties is scalable and has the potential to keep up with the pace of technology advances. Then we discuss some of the trends that will enforce significant changes on current design methodologies and techniques. Finally, w...

The problem of contention for routers and links is one of the critical problems caused by the NoC (network-on-chip) reuse approach in testing NoC systems. In this paper, we propose zigzag connected subgraph partition approach to avoid the contention for routers and links in NoC testing. Then, a MMQEA (multi-population multi-nary quantum-inspired evolutionary algorithm) strategy, which incorpora...

Network-on-Chip(NoC) has been proposed as a solution for addressing the communication infrastructure design challenges of future high-performance nanoscale architecture of SoCs. IrNIRGAM is a discrete event, cycle accurate simulator targeted at irregular topology based Network on Chip (NoC) research. The generic, modular, and extensible framework of IrNIRGAM provides substantial support to expe...

Network-on-Chip (NOC) has been proposed as an attractive alternative to traditional dedicated wire to achieve high performance and modularity. Power and Area efficiency is the most important concern in NOC design. Small optimizations in NoC router architecture can show a significant improvement in the overall performance of NoC based systems. Power consumption, area overhead and the entire NoC ...

It is with great pleasure that we introduce the special issue on Networks-on-Chip (NoC) to the readers of the Journal of Parallel and Distributed Computing (JPDC). This special issue consists of eight peer-reviewed papers that cover a wide spectrum of topics in NoC design. Large multicore-based and multiprocessor-based systems-onchip (MPSoC) architectures will easily consist of billions of tran...

Networks-on-Chip (NoC) is recently proposed as an alternative to the on-chip bus to meet the increasing requirement of complex communication needs in Systems-on-Chip (SoC). Using on-chip interconnection networks in place of ad-hoc global wiring, structures the top level wires on a chip and facilitates modular design. The structured network wiring gives well-controlled electrical parameters that...

In the era of many-core chips, problem power density is a serious challenge. This particularly important in Network-on-Chip (NoC)-based systems, where application mapping determines resulting patterns and workload distribution across entire chip. Despite this fact, majority algorithms focus on performance, are largely ignored. work investigates problem. Three different pattern metrics with scop...

Network on Chip (NoC) is proposed as a promising technology to address the communication challenges in deep sub-micron era. NoC brings network-based communication into the on-chip environment and tackles the problems like long wire complexities, bandwidth scaling and so on. After more than a decade's evolution and development, there are many NoC architectures and solutions available. Neverthele...

Systems-on-Chip (SoC) architectures have been shifting from single-core to multi-core solutions, and they are at present evolving towards many-core ones. Network-on-Chip (NoC) is considered as a promising interconnection scheme for many-core SoCs since it offers better scalability than traditional bus-based interconnection. In this work, we have developed a fast simulator of NoC architectures u...