Network-on-Chip (NoC) is viewed as a viable substitution for traditional interconnection networks to achieve high performance, communication efficiency and reliability in complex VLSI architectures at deep sub micron. Achieving high performance, power efficiency with optimum area is a target for any routing algorithm in NoC. In this paper, we propose a novel routing scheme named ‘ERA’, which of...

This paper addresses application mapping technique targeted for large-scale Network-on-chip (NoC). The increasing number of intellectual property (IP) cores in multi-processor System-on-Chips (MPSoCs) makes NoC application mapping more challenging to find optimum core-to-topology mapping. The factorial increase in possible mappings space requires a mapping algorithm to efficiently look for pote...

Currently, most of Network on-Chip (NoC) architectures have some limitation in routing decisions. And it makes router nodes overloaded, and sequentially forms deadlock, livelock and congestion. A simple unbuffered router microarchitecture for S-mesh NoC architecture is proposed in this paper. Unbuffered router transforms message without making routing decision. Simulation results showed that S-...

To alleviate the complex communication problems arising in the network-on-chip (NoC) architectures as the number of on-chip components increases, several novel interconnect infrastructures have been recently proposed to replace the traditional on-chip interconnection systems that are reaching their limits in terms of performance, power and area constraints. Wireless NoC (WiNoC) is among the mos...

A main challenge for Network-on-Chip (NoC) design is to select a network architecture that suits a particular application. NNSE enables to analyze the performance impact of NoC configuration parameters. It allows one to (1) configure a network with respect to topology, flow control and routing algorithm etc.; (2) configure various regular and application specific traffic patterns; (3) evaluate ...

At present, typical application-specific NoC systems often integrate a number of heterogeneous components which have varied functions, sizes and communication requirements. Instead of regular topology networks, constructing irregular mesh topology network on chip (NoCs) becomes an attractive approach to building future NoC systems with irregular structure. Deadlock-free routing control algorith...

Two network-on-chip (NoC) designs are examined and compared in this paper. One design applies a bidirectional ring connection scheme, while the other design applies a code-division multiple-access (CDMA) connection scheme. Both of the designs apply globally asynchronous locally synchronous (GALS) scheme in order to deal with the issue of transferring data in a multiple-clockdomain environment o...

In this article, I present the biological backgrounds of microarray, ChIP-chip and ChIPSeq technologies and the application of computational methods in reverse engineering of gene regulatory networks (GRNs). The most commonly used GRNs models based on Boolean networks, Bayesian networks, relevance networks, differential and difference equations are described. A novel model for integration of pr...

In this paper, a Clustered NOC (C-NOC) is introduced to improve the performance of Hermes-NOC (H-NOC) in group communication. Each C-NOC switch has eight bi-directional ports connected to four neighbor switches and four local ports. With the same (IP) cores in both H-NOC and C-NOC networks, the ordinal size of C-NOC is 75% less than H-NOC. In corner-to-corner communication, C-NOC operates 29% f...

In a latest network-on-chip design, several cores and intellectual properties can be integrated into a one chip. For high-performance interconnects, designers rapidly adopt advance interconnect protocols that support mechanisms of parallel accessing, including outstanding transactions and out-of-order complete of transactions. To produce these novel mechanisms, a master tag an ID to each transa...