Custom microchips housing many simple processors have long been used in the design ofmassively parallel computers. Commercially available SIMD!arallel systems of the late 1980s already containe tens of bit-serial processors on each chip and more recent products offer hundreds of processors per chip. Use of microchips housing multiple general-purpose processors. with large memories. has also bee...

Multi-level Intelligent Synthesis and Simulation Environment (MISSE) is an object-oriented, top-down, high-level design environment for multiprocessor systems. Three important aspects of multiprocessor system design: modeling, synthesis, and simulation are supported in MISSE. First, multiprocessor systems are hierarchically classified and system parts modeled as objects with interrelationships....

This paper presents a general theory for modeling and designing fault-tolerant multiprocessor systems in a systematic and efficient manner. We are concerned here with structural fault tolerance, defined as the ability to reconfigure around faults in order to preserve the interconnection structure of a multiprocessor. We represent multiprocessor systems by graphs whose node sets denote processor...

The well-known Clos network has been extensively used for telephone switching, multiprocessor interconnection and data communications. Much work has been done to develop analytical models for understanding the routing blocking probability of the Clos network. However, none of the analytical models for estimating the blocking probability of this type of network have taken into account the very r...

Cluster systems are getting increasingly popular since they provide large computational power at a reasonable price. The cluster nodes are often SMPs with a small number of processors that can access a shared address space. The nodes are connected by a network like Myrinet or SCI, so the global address space is distributed. In this paper, we present a new programming model for such clusters of ...

The MIT Alewife project evolved out of exploratory work at Stanford on directory schemes for cache coherence [1] (also included in this issue). Using data from small bus-based multiprocessors, this early work demonstrated that directory schemes were as efficient as bus-based snooping protocols, and that by distributing directories along with main memory, they could provide the foundations for a...

In a distributed shared memory (DSM) multiprocessor, the processors cooperate in solving a parallel application by accessing the shared memory. The latency of a memory access depends on several factors including the distance to the nearest valid data copy, data sharing conditions, and traffic of other processors. To provide a better understanding of DSM performance and to support application tu...

Recent advances in FPGA (Field-Programmable Gate Array) technologies have made feasible the implementation of low-cost parallel computing platforms for highperformance matrix computations. Compared to conventional multiprocessor systems, the resulting MultiProcessors-On-a-Programmable-Chip (MPoPCs) can provide unique advantages and opportunities in both software and hardware. It is shown in thi...

In this paper, three new node-ranking schemes for the star graph are presented and evaluated. These node-ranking schemes efficiently ‘‘embed’’ grids, pipelines, and reconfigurable multiple ring networks (cases of torus networks). These schemes improve similar known results on the star graph. They also allow efficient mapping of a wide class of algorithms into the star graph and hence facilitati...