Approximate multipliers are widely being advocated for energy-efficient computing in applications that exhibit an inherent tolerance to inaccuracy. However, the inclusion of accuracy as a key design parameter, besides the performance, area and power, makes the identification of the most suitable approximate multiplier quite challenging. In this paper, we identify three major decision making fac...

Based on the shifted polynomial basis (SPB), a high efficient bit-parallel multiplier for the field GF(2m) defined by an equallyspaced trinomial (EST) is proposed. The use of SPB significantly reduces time delay of the proposed multiplier and at the same time Karatsuba method is combined with SPB to decrease space complexity. As a result, with the same time complexity, approximately 3/4 gates o...

With the end goal of implementing optimal Reed-Solomon error control decoders on FPGAs, we characterize the FPGA performance of several finite field multiplier designs reported in the literature. We discover that finite field multipliers optimized for VLSI implementation are not optimized for FPGA implementation. Based on this observation, we discuss the relative merits of each multiplier desig...

In this paper, a technique for realizing a floating capacitance multiplier based on the use of dual output current conveyors and grounded capacitance is proposed. Its multiplication factor can be tuned by changing the ratio of resistors. Moreover, the circuit is easily modified to electronically tunable floating capacitance multiplier by using current controlled conveyor. Simulation results are...

This paper presents a synthesisable VHDL model for a generalised multiplier capable of performing multiplication of both sign-magnitude and two’s complement operands. The multiplier is testable with a constant number of test vectors irrespective of operand word-lengths thereby reducing automatic test generation, simulation and testing times. The model has been used successfully for generating m...

We put the known results on the antipode of a usual quasitriangular Hopf algebra into the framework of multiplier Hopf algebras. We illustrate with examples which can not be obtained by using classical Hopf algebras. The focus of the present paper lies on the class of the so-called G-cograded multiplier Hopf algebras. By doing so, we bring the results of quasitriangular Hopf group-coalgebras (a...

this paper presents results of applying a new approach on 2d inversion of magnetotelluric (mt) data in order to enhance resolution and stability of the inversion results. due to non-linearity and limited coverage of data acquisition in an mt field campaign, minimizing the error by linearization of the problem in least squares inversion usually leads to an ill-posed problem. in general, an inver...

In this paper, we will study the theory of cyclic homology for regular multiplier Hopf algebras. We associate a cyclic module to a triple $(mathcal{R},mathcal{H},mathcal{X})$ consisting of a regular multiplier Hopf algebra $mathcal{H}$, a left $mathcal{H}$-comodule algebra $mathcal{R}$, and a unital left $mathcal{H}$-module $mathcal{X}$ which is also a unital algebra. First, we construct a para...

A rapid and proficient in power requirement multiplier is always vital in electronics industry like DSP, image processing and ALU in microprocessors. Multiplier is such an imperative block w ith respect to power consumption and area occupied in the system. In order to meet the demand for high speed, various parallel array multiplication algorithms have been proposed by a number of authors. The ...

A special moduli set Residue Number System (RNS) of high dynamic range (DR) can speed up the execution of very large word-length repetitive multiplications found in applications like public key cryptography. The modulo 2 − 1 multiplier is usually the noncritical datapath among all modulo multipliers in such high-DR RNS multiplier. This timing slack can be exploited to reduce the system area and...