Conventionally, the test of multiport memories is considered difficult because of the complex behavior of the faulty memories and the large number of inter-port faults. This paper presents an efficient approach for testing and diagnosing multiport RAMs. Our approach takes advantage of the higher access bandwidth due to the increased number of read/write ports, which also provides higher observa...

Current studies of fault interaction lack sufficiently long earthquake records and measurements of fault slip rates over multiple seismic cycles to fully investigate the effects of interseismic loading and coseismic stress changes on the surrounding fault network. We model elastic interactions between 97 faults from 30 earthquakes since 1349 A.D. in central Italy to investigate the relative imp...

Context: Software developers spend a significant amount of time fixing faults. However, not many papers have addressed the actual effort needed to fix software faults. Objective: The objective of this paper is twofold: (1) analysis of the effort needed to fix software faults and how it was affected by several factors and (2) prediction of the level of fix implementation effort based on the info...

We describe the application of the following tools to ITC-99 benchmark circuits. Deterministic test generation: The test generation procedure MIX [1], and its extension MIX + [2], combines several test generation approaches to derive test sequences exhibiting very high fault coverages at relatively low CPU times. It includes a simulation-based test generation procedure based on LOCSTEP [3], a d...

Resilient topologies and routing are among the important topics that were addressed within the HIDENETS project and have been the focus of task 1 of Work Package 3 ‘Resilient Communication’. This document provides the results of the work in this area. The document has the following content: (1) The HIDENETS network architecture is described, introducing the relevant terminology and the use case...

Extended Abstract Right timing of complex digital circuits and systems in nanotechnology need careful design steps and testing. Incorrect timing can be caused during design or manufacturing processes. Incorrect timing is manifested as delay faults. The delay faults in digital circuit testing are more and more important due to huge number of gates and lines integrated on a chip specifically in n...

Faults in large-scale chemical plants could occur at a process level although, more often, faults occur at the instrument and equipment level. A failure in an equipment could quickly propagate throughout the process resulting in leaks, fires and explosions causing loss of life, capital invested and production downtime. Attempting to monitor the overall process for identifying such instrument an...

Process allocation is important for fault-tolerant multi-computer systems since it directly aaects the performance and dependability of the system. In this paper , we consider load-balancing process allocation for fault-tolerant systems that balances the load before as well as after faults start to degrade the performance of the system. We show two schemes to tolerate multiple faults in the pas...