Multi-modal test execution allows execution of the same test against various layers of a software system, e.g. the GUI layer, the web service layer and the business logic layer. Multi-modal test execution helps with identifying the location of software bugs during debugging and maintenance as well as in tracking the progress of the development effort. This paper presents a method that effective...

The paper presents a novel Optical Network on Chip (ONoC) relying on the multi-level optical layer design paradigm and called “OMNoC”. The proposed ONoC relies on multi-level microring resonator allowing efficient light coupling between superposed waveguides. Such microring resonator avoids using waveguide crossing, which contribute to reduce propagation losses. Preliminary experimental results...

The Ti/TiN multi-layer film was prepared on the depleted uranium (DU) substrate by cathodic arc ion plating equipment. The character of multi-layer film was studied by SEM, XRD and AES, revealed that the surface was composed of small compact particle and the cross-section had a multi-layer structure. The fretting wear performance under different frequencies was performed by a MFT-6000 machine w...

The following report presents the preliminary results and theoretical backgrounds of a multi-layer evolutionary mechanism. The project aims at developing a mechanism for automated agent design within a pre-designed multi-layer architecture. The core mechanism used in the experiments is a Genetic Programming algorithm working in a specially designed condition-action rules system. There is descri...

In classical Cluster Editing we seek to transform a given graph into a disjoint union of cliques, called a cluster graph, using the fewest number of edge modifications (deletions or additions). Motivated by recent applications, we propose and study Cluster Editing in multi-layer graphs. A multi-layer graph consists of a set of simple graphs, called layers, that all have the same vertex set. In ...

This paper describes the implementation of the L3 maze routing accelerator in an FPGA. L3 supports fast single-layer and multi-layer routing, preferential routing, and rip-up-and-reroute. A 16 X 16 single-layer and 4 X 4 multi-layer router that can handle 2-16 layers have been implemented in a low-end Xilinx XC2S300E FPGA. Larger arrays are currently under construction.

The design of robust and area efficient power distribution networks for high speed, high complexity integrated circuits has become a challenging task. The integrity of the high frequency signals depends upon the impedance characteristics of the on-chip power distribution networks. The electrical characteristics of these multi-layer power distribution grids and the relevant design implications a...

This paper reports a bimorph piezoelectric vibration energy harvester incorporating multiple PZT layers. The advantage of a multi-layer generator is that it produces a higher power than a single-layer generator having the same total thickness. In addition, a lower voltage is required to polarize a multi-layer generator reducing the risk of breakdown during polarization. Moreover, the optimum re...

An artificial neural network has been used to determine the volume flux and rejections of Ca2+ , Na+ and Cl¯, as a function of transmembrane pressure and concentrations of Ca2+, polyethyleneimine, and polyacrylic acid in water softening by nanofiltration process in presence of polyelectrolytes. The feed-forward multi-layer perceptron artificial neural network including an eight-neuron hidde...