نتایج جستجو برای: mixed standby
تعداد نتایج: 221961 فیلتر نتایج به سال:
Comparision on Different Domino Logic Design for High- Performance and Leakage-Tolerant Wide OR Gate
Dynamic logic circuits are used for high performance and high speed applications. Wide OR gates are used in Dynamic RAMs, Static RAMs, high speed processors and other high speed circuits. In spite of their high performance, dynamic logic circuit has high noise and extensive leakage which has caused problems for the circuits. To overcome these problems Domino logic circuits are used which reduce...
Miniature sensor nodes are ideal for monitoring environmental conditions in emerging applications such as oil exploration. One key requirement for sensor nodes is embedded non-volatile memory for compact and retentive data storage in the event that the sensor power source is exhausted. Non-volatile memory also allows for near-zero standby power modes, which are particularly challenging to achie...
Reliability issues for various technical systems are discussed and focus is directed towards distributed systems, where communication facilities are vital to maintain system functionality. Reliability in communication subsystems is considered as a resource to be shared among a number of logical connections and a reliability management framework is suggested. We suggest a network layer level rel...
In this paper, probabilistic models for two dissimilar redundant systems with replacement at each common cause failure have been developed to analyze and compare some reliability characteristics. Two configurations are studied under the assumption that each system is replaced at the occurrence of common cause failure. Configuration I is a 3-out-of-4 cold standby system, while configuration II i...
Suppressing the leakage current in memories is critical in low-power design. By reducing the standby supply voltage (VDD) to its limit, which is the data retention voltage (DRV), leakage power can be substantially reduced. This paper models the DRV of a standard low leakage SRAM module as a function of process and design parameters, and analyzes the SRAM cell stability when VDD approaches DRV. ...
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