Presented here is a lObit SAR ADC working over a wide supply range of 5.W to 2.W. The circuit is built in a CMOS process with Metal-Poly capacitors. Issues related to low voltage sampling circuitry design and low voltage high speed comparator design are discussed. Silicon evaluation results are presented.

Design techniques for robust, low-power CMOS circuits are presented for applications in wireless cubicmillimeter sensor nodes. First, the design of a two-transistor voltage reference is described and its characteristics simulated. Then, a low-voltage toggle flip-flop circuit is discussed and modeled using standard switching theory. Finally, a study of the battery used to power the cubic-millime...

This paper presents the design of a low-power voltage reference, bias current and the supply voltage for a 9-bit fully differential ADC. The references, power supply circuits and the ADC are integrated in one circuit, i.e. chip. The proposed chip is implemented in the UMC 0.18 μm CMOS process and occupies 800×700 μm. The circuit supply voltage V DD is obtained from the external RF signal. When ...

A new circuit technique for voltage gain enhancement in CMOS op amp design suitable for low voltage and high speed operation is presented in this paper. A negative conductance is used to cancel the positive output conductance of an amplifier thereby reducing the total equivalent output conductance and increasing the voltage gain of the amplifier. The negative conductance is derived from the out...

The advancement in the integrated circuit design has developed the demand for low voltage portable analog devices in the market. This demand has increased the requirement of the low-power RF transceiver. A low-power phase lock loop (PLL) is always desirable to fulfill the need for a low power RF transceiver. This paper deals with the designing of the low power transconductance- capacitance (Gm-...

A dynamic phasor model for lowand medium-voltage distribution grids is presented. This model accurately represents the transient dynamics of this type of grid, and its low order makes it well suited for control design. A novel fixed-structure, robust control design method based on convex optimization is then used to design a decentralized low-order controller that shows a significantly improved...

Two new electrostatic discharge (ESD) protection design by using only 1 × VDD low-voltage devices for mixedvoltage I/O buffer with 3 × VDD input tolerance are proposed. Two different special high-voltage-tolerant ESD detection circuits are designed with substrate-triggered technique to improve ESD protection efficiency of ESD clamp device. These two ESD detection circuits with different design ...

In this paper, a new low-voltage low-power CMOS 1-bit full adder circuit is proposed. The proposed full adder can provide a full voltage swing at a low supply voltage and offers superior performance in both power and speed than the conventional full adder, the transmission full adder, and the recent low-voltage full adder. Based on the simulation results performed by HSPICE, the new low-voltage...

This study presents a four-phase interleaved high voltage conversion ratio bidirectional DC-DC converter circuit based on coupled inductors and switched capacitors, which can eliminate the defects of conventional high voltage conversion ratio bidirectional DC-DC converters in terms of high-voltage/current stress, less efficiency and low-power limitation. Parallel channels are used to reduce cur...