Abnormal IDDQ (Quiescent VDD supply current) indicates the existence of physical damage in a circuit. Using this phenomenon, a CAD-based fault diagnosis technology has been developed to analyze the manufacturing yield of logic LSI. This method to detect the fatal defect fragments in several abnormalities identified with wafer inspection apparatus includes a way to separate various leakage fault...

Recently reported logic style comparisons based on full-adder circuits claimed complementary pass-transistor logic (CPL) to be much more power-efficient than complementary CMOS. However, new comparisons performed on more efficient CMOS circuit realizations and a wider range of different logic cells, as well as the use of realistic circuit arrangements demonstrate CMOS to be superior to CPL in m...

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SER is one of the problems associated with continued scaling. Traditionally, logic SER is solved at the system/architecture level (e.g., DMR, TMR, checkpointing/recovery). There has also been some work at the process level (e.g., SOI), but recently, there is also some research work on circuit level (e.g., cell hardening, BISER), but there has not been a wide spread adoption yet. Can logic SER b...

A 2-digit higher radix analog-to-digital converter (ADC) circuit consisting of a combination of a pipelined ADC and a set of cascaded current comparator cell has been proposed. The ADC generates multi-valued logic outputs rather than the conventional binary output system. The design is implemented using 0.25μm CMOS process. The performance analysis of the design shows desirable performance para...

An Energy Efficient Feedthrough Logic (EE-FTL) is proposed in this paper to reduce the power consumption for low power applications. The EE-FTL is well suited to arithmetic circuits where the critical path is made of a large cascade of inverting gates. It has a unique characteristic where the output is pre-evaluated before the inputs from the preceding stage are ready. The proposed logic style ...

In this paper we propose two buffer circuits for footed domino logic circuit. It minimizes redundant switching at the output node. These circuits prevent propagation of precharge pulse to the output node during precharge phase which saves power consumption. Simulation is done using 0.18μm CMOS technology. We have calculated the power consumption, delay and power delay product of proposed circui...

Compared with classical algorithms, quantum algorithms can show the advantage of exponential speedup in solving some problems. Solving NAND-Tree problem is a typical example, which be speed up exponentially by walk. This scheme groundbreaking due to universality negative-AND (NAND) gate. In fact, NAND gate also universal for computation, making it an important target development. Herein, onto c...