|Interconnect between a CMOS driver and receiver can be modeled as a lossy transmission line in high speed CMOS VLSI circuits as transition times become comparable to or less than the time of ight delay of the signal through the interconnect. In this discussion, a linear resistor model is used to approximate the CMOS driver stage, and the CMOS receiver is modeled as a capacitor. A closed form e...

Interconnect testing in a SoC environment is a new area of research. It represents a further development of traditional board-level testing with respect to the new interconnect paradigm, new fault models, and required high level of autonomy. This article analyzes available interconnect self-test solutions and comes up with a new BIST scheme for at-speed testing of SoC interconnect. We adapt a r...

ed to the one shown in Figure 5 (a), where the processor block on the left hand of the interconnect corresponds to the AFS server, Storage Node, VFS server, etc, For ease of discussion, in the remaining of the paper, we use a unified term "storage node" to refer to these nodes. The main purpose for a storage node in a cluster is to manage storage devices attached to it and provide data services...

In this paper, we study the modeling and layout optimization for on-chip interconnect structures to minimize the inductive coupling. We first investigate the characteristics of mutual (as well as self) inductance for coplanar, micro-stripline, and stripline structures, and examine the effectiveness of design freedoms such as wire sizing, spacing, and shielding. We then propose formula-based mod...

Due to continuous technology scaling, the interconnect delay and power reduction is becoming one of the most important design challenges. In this paper, we present a novel algorithm for simultaneous multilayer interconnect spacing so that on the one hand the total power of interconnect is reduced and on the other hand, delay constraints are not violated. We first present an optimization problem...

An FPGA-based reconfigurable system may contain boards of FPGAs which are reconfigured for different applications and must work correctly. This paper presents a novel approach for rapidly testing the interconnect in the FPGAs each time the system is reconfigured. A lowcost configuration-dependent test method is used to both detect and locate faults in the interconnect. The “original configurati...

In nanometer scale integrated circuits, concurrent insertion of repeaters and sequential elements into the global interconnect lines has been proposed to support multicycle communication—a concept known as interconnect pipelining. The design targets of an interconnect-pipelining scheme are to ensure high reliability, low-power consumption, and less delay cycles. This paper presents an in-depth ...

The “chicken-egg” dilemma between VLSI interconnect timing optimization and delay calculation suggests an iterative approach. We separate interconnect timing transformation as Hanan grafting and non-Hanan sliding, and reveal generally negligible contribution of non-Hanan sliding. We propose a greedy iterative interconnect timing optimization algorithm called Q-Tree. Our experimental results sho...

Most reconngurable multi-fpga architectures have a programmable interconnection network that can be reconngured to implement diierent interconnection patterns between the fpgas and memory devices on the board. Partitioning tools for such architectures must produce the necessary pin-assignments and interconnect connguration stream that correctly implement the partitioned design. We call this pro...

Demand of power efficient circuits has grown significantly due to fast growth of battery operated portable applications. Though, subthreshold operation of device shows huge potential towards satisfying the ULP requirement, it holds many challenging design issues. As integration density of interconnect increases at every technology node, increased delay and crosstalk become more challenging desi...