Reactors based on particle suspensions for the capture, conversion, storage, and use of solar energy as H 2 are projected to be cost-competitive with fossil fuels. In light of this, this review paper summarizes state-of-the-art particle light absorbers and cocatalysts as suspensions (photocatalysts) that demonstrate visible-light-driven water splitting on the laboratory scale. Also presented ar...

consider search designs for searching one nonzero 2- or 3-factor interaction under the search linear model. in the noisy case, search probability is given by shirakura et al. (ann. statist. 24(6) (1996) 2560). in this paper some new properties of the searching probability are presented. new properties of the search probability enable us to compare designs, which depend on an unknown parameter ?...

This paper presents a new satisfiability (SAT) modulo Theory (SMT) solver, STABLE, for formulas of the quantifierfree logic over fixed-sized bit vectors (QF-BV). As the primary application domain for STABLE we target an SMT-based property checking flow for System-on-Chip (SoC) designs. STABLE integrates a computer-algebra-based engine which provides algorithms for proving arithmetic problem par...

The paper describes several complementary algorithms for power-aware logic optimization: o SimSwitch is an efficient sequential simulator for estimating switching activity of signals in large sequential designs. o PowerMap uses switching activity to make better decisions during power-aware technology mapping. o PowerDC is a resynthesis algorithm that eliminates wires with high switching activit...

The adoption of register-transfer level (RTL) sign-off in ASIC design methodologies, and the increasing scale of system-on-chip integration, are leading to unprecedented accuracy and efficiency demands on RT-level estimation tools. In this work, we focus on the deployment of a simulation-based RTL power estimation tool in a commercial design flow, and describe several enhancements that improve ...

Model checking technologies have been applied to hardware verification in the last 15 years. Pioneering work has been conducted in Intel since 1990 using model checking technologies to build industrial hardware verification systems. This paper reviews the evolution and the success of these systems in Intel and in particular it summarizes the many challenges and learning that have resulted from ...

The application of the Industrial Ethernet brings up issues of both the reliability and behaviour of the networks under a demanded load, while preserving the permitted time delay in the whole network. We propose an algorithm that designs the network topology, which meets the required fault tolerance and allows reliable communication between the parts of the control system. For this purpose, we ...

Self-adaptive systems need to monitor themselves, to check their internal behaviour and design assumptions about runtime inputs and conditions. This kind of monitoring for self-adaptive systems can include collecting statistics about such systems themselves which can be computationally intensive (for detailed statistics) and hence time consuming, with possible negative impact on selfadaptive re...

In this paper, we present a complete chip design method which incorporates a soft-macro resynthesis method in interaction with chip oorplanning for area and timing improvements. We develop a timing-driven design ow to exploit the interaction between HDL synthesis and physical design tasks. During each design iteration, we resynthesize soft macros with either a relaxed or a tightened timing cons...