In the present paper we have done a comparative analysis of Dual Gate MOSFET having split gate architecture and conventional Dual Gate MOSFET architecture. Simulations have been performed using SILVACO-ATLAS tool, which shows significant improvement in characteristic of split gate architecture in comparison to the conventional structure. The split gate architecture consist two different materia...

This paper presents a way to enhance the Differential Current-Switch Threshold Logic gate (DCSTL) in order to allow the gate to perform more complex functions. This enhancement is achieved by replacing the MOS-transistors at the dataand threshold mapping bank of the DCSTL gate with neuronMOS transisors. First, we introduce the neuronMOS-enhanced DCSTL gate. Then, the results of HSPICE simulatio...

---In this paper a thorough investigation of resistive logic RCJL gate has been made. The current equations of this gate at each stage have been deduced. The dynamic response of this gate has been obtained by the computer-simulation. Our concept of turn-on delay has been introduced. The effect of overdrive current on turn-on delay for resistive logic gate has been shown. This will provide a bet...

Degradation phenomena due to hot carrier stress conditions were investigated in double-gate polysilicon thin film transistors fabricated by sequential lateral solidification (SLS). We varied the hot carrier stress conditions at the front gate channel by applying various voltages at the back-gate. Thus, we investigated the device electrical performance under such stress regimes. As a conclusion,...

Gate and drain current noise investigations are performed on nMOS transistors with HfO2 gate oxides. The drain noise magnitude allows extraction of the slow oxide trap density Nt(EF) ranging from 3 to 7 10 eV cm. These values are about 50 times higher than for SiO2 dielectrics. The 1/f gate current noise component is a quadratic function of the gate leakage current. The gate noise parameter KGC...

This work describes the improved uniformity of short gate length (sub100nm) T-gate lithography observed for InP HEMT devices through the development of a nonannealed ohmic contact process. The incorporation of such a process allows the reversal of ohmic and gate levels as part of a standard device process flow. This eliminates fluctuations in the gate geometry that result from the spinning of g...

High-k gate dielectrics are used to suppress excessive transistor gate leakage and power consumption could speed up the introduction of metal gates in complementary metal oxide semiconductor (CMOS) transistors. Many new oxides are being evaluated as gate dielectrics, such as Al2O3, Y2O3, La2O3, Gd2O3, HfO2, ZrO2, and TiO2, BaZrO3, ZrSiO4 and HfSiO4. Ru, RuO2 and SrRuO3 gate electrodes grown on ...