In processors that do not support floating-point instructions, using fixed-point arithmetic instead of floating-point emulation trades off computation accuracy for execution speed. This trade-off is often profitable. In many cases, like embedded systems, low-cost and speed bounds make it the only acceptable option. We present an environment supporting fixed-point code generation from C programs...

The accuracy of the multiplication depends on the precision of the multiplier. The variable precision floating point multiplier will have more accuracy when compared with the fixed precision multiplier. In this paper a variable precision floating point multiplier is considered. An effective BIST test pattern generator for variable precision floating point multiplier is proposed. A BIST TPG cons...

Keywords: Floating-point arithmetic FPGAs Library of operators High performance The high integration density of current nanometer technologies allows the implementation of complex floating-point applications in a single FPGA. In this work the intrinsic complexity of floating-point operators is addressed targeting configurable devices and making design decisions providing the most suitable perfo...

Through the study of floating quantifiers in a variety of languages, I demonstrate that floating quantification is not a uniform phenomenon and outline a series of puzzles that force us to adopt a two-part analysis. I argue that certain floating quantifiers are related to their nominal associate by syntactic transformation (the stranding approach, Sportiche 1988; Miyagawa 1989) and that others ...

The novel method is to optimize coarse-grained floating point units (FPUs) in a hybrid FPGA by employing common sub graph extraction to determine the number of floating point adders / subtracters (FAs), multipliers (FMs) and word blocks (WBs) in the FPUs. Single precision FP adders / subtracters (FAs) and FP multipliers (FMs), with normalization are generated using standard cell library design ...