This paper is devoted to the design of a 258-bit multiplier for computing pairings over Barreto-Naehrig (BN) curves at 128-bit security level. The proposed design is optimized for Xilinx field programmable gate array (FPGA). Each 258-bit integer is represented as a polynomial with five, 65 bit signed integer, coefficients. Exploiting this splitting we designed a pipelined 65-bit multiplier base...

Multiple-input-multiple-output (MIMO) technique is often employed to increase capacity in comparing to systems with single antenna. However, the computational complexity in evaluating channel capacity or transmission rate (data rate) grows proportionally to the number of employed antennas at both ends of the wireless link. Recently, the QR decomposition (QRD) based detection schemes have emerge...

Scalar replacement or register promotion uses scalar variables to save data that can be reused across loop iterations, leading to a reduction of the number of memory operations at the expense of a possibly large number of registers. In this paper we present a compiler data reuse analysis capable of uncovering and exploiting reuse opportunities for array references that exhibit Multiple-Inductio...

Abstract In this work, multi-function vehicle bus (MVB) controller-based Field Programmable Gate Array (FPGA) and MVB manager based on the real-time multitasking operating system were explored developed. The function of controller data link layer was realised by using FPGA. embedded uCOS-II applied to development manager’s processing data, device state management, message management function. n...

A comparison of linear and quadratic transform implementation on field programmable gate array (FPGA) is presented. Popular namely Stockwell Transform Smoothed Pseudo Wigner Ville Distribution (SPWVD) from Quadratic transforms considered for the FPGA. Both are coded in Verilog hardware description language (Verilog HDL). Complex calculations transformation performed by using CORDIC algorithm. F...

Advancements in parallel and cluster computing have made many complex Monte Carlo simulations possible in the past several years. Unfortunately, cluster computers are large, expensive, and still not fast enough to make Monte Carlo useful for calculations requiring a near real time evaluation period. For Monte Carlo simulations, a small computational unit called a Field Programmable Gate Array (...

With the expansion of system scale and reduction in simulation step size, design a power real-time platform faces many difficulties. The interactive operation presents characteristics phased centralized. This paper proposes selecting appropriate method for each sub-network according to requirements, can be changed with change requirements process. In order process, high flexibility hybrid archi...

A design of systolic array-based Field Programmable Gate Array (FPGA) parallel architecture for Basic Local Alignment Search Tool (BLAST) Algorithm is proposed. BLAST is a heuristic biological sequence alignment algorithm which has been used by bioinformatics experts. In contrast to other designs that detect at most one hit in one-clock-cycle, our design applies a Multiple Hits Detection Module...