We present an analytical technique that uses fault injection data for estimating the coverage of concurrent error detection mechanisms in microprocessors. A major problem in such estimations is that the coverage depends on the program executed by the microprocessor as well as the input sequence to the program. We propose a method that predicts the error coverage for a specified input sequence b...

Conventional automatic test-pattern generation (ATPG) cannot effectively handle designs employing blocks whose implementation details are either unknown, unavailable, or subject to change. Realization-independent block testing for cores (RIBTEC), a novel ATPG program for such designs, is described, which employs a functional (behavioral) fault model based on a class of nonexhaustive “universal”...

In this paper, the natures of random and pseudo-random input sequences and their influence on permanent and intermittent fault detecting are analyzed. The aliasing fault coverage between the pseudo-random and random sequences is estimated. The activity probability features of the intermittent faults are considered. The selftest circuits of the intermittent faults are illustrated. The experiment...

The quality of tests, in terms of fault coverage and test length, is strongly dependent on the used fault models. This paper presents realistic fault models for multiport memories with p ports, based on defect injection and SPICE simulation. The results show that the fault models for -port memories consist of p classes: single-port faults, two-port faults,..., -port faults. In addition, the pap...

Ensuring that a distributed system meets its prescribed specification is a growing challenge that confronts software developers and system engineers. Meeting this challenge is particularly important for applications with strict dependability and/or timeliness constraints. We have developed a software fault injection tool, called ORCHESTRA, for testing dependability and timing properties of dist...

The ever increasing trend to reduce DPM levels of memories requires tests with very high fault coverage and low cost. This paper describes an important fault class, called dynamic faults, that cannot be ignored anymore. The dynamic fault behavior can take place in the absence of the static fault behavior, for which the conventional memory tests have been constructed. The concept of dynamic faul...

Handshake circuits form a special class of asynchronous circuits that has enabled the industrial exploitation of the asynchronous potential such as low power, low electromagnetic emission, and increased cryptographic security. In this paper we present a test solution for handshake circuits that brings synchronous test-quality to asynchronous circuits. We add a synchronous mode of operation to h...

A new on-chip embedding mechanism to improve fault coverage in scan-based delay test is proposed. A major problem of scan-based delay test techniques is that they may not provide good fault coverage as many valid test pattern pairs cannot be launched. In the proposed method, the initialization vector is shifted into the scan chain, and then the activation vector is generated by selectively inve...

A number of analytical software reliability models have been proposed for estimating the reliability growth of a software product. In this paper we present an Enhanced nonhomogeneous Poisson process (ENHPP) model and show that previously reported Non-Homogeneous Poisson Process (NHPP) based models, with bounded mean value functions, are special cases of the ENHPP model. The ENHPP model differs ...

In the area of testing communication systems, the interfaces between systems to be tested and their testers have great impact on test generation and fault detectability. Several types of such interfaces have been standardized by the International Standardization Organization (ISO). A general distributed test architecture, containing distributed interfaces, has been presented in the literature f...