This letter demonstrates a p-type raised source-and-drain (raised S/D) junctionless thin-film transistors (JL-TFTs) with a dual-gate structure. The raised S/D structure provides a high saturation current (>1 μA/μm). The subthreshold swing (SS) is 100 mV/decade and the drain-induced barrier lowering (DIBL) is 0.8 mV/V, and the I on/I off current ratio is over 10(8) A/A for L g = 1 μm. Using a th...

Gate depletion and boron penetration through thin gate oxide place directly opposing requirements on the gate engineering for advanced MOSFET’s. In this paper, several important issues of deep-submicron CMOS transistor gate engineering are discussed. First, the impact of gate nitrogen implantation on the performance and reliability of deep-submicron CMOSFET’s is investigated. The suppression of...

A InGaP/InGaAs/GaAs dual channel pseudomorphic HEMT (DCPHEMT) with interesting triple doped sheets having gate length 800nm is modeled and simulated by using 2-dimensional simulation package ATLAS from Silvaco. Different DC and microwave performances of the above device are analyzed and investigated to judge the potential of the device for highperformance digital device applications. Due to the...

A dual-chip architecture is presented for gate dispersive readout of charge states in quantum electronic devices, which outperforms previous fully-integrated systems and may facilitate scaling spin-qubits.

This paper focuses on the noise behavior of nMOSFETs with high-k gate dielectrics (SiON/HfO2) with an equivalent oxide thickness of 0.92 nm and using metal (TiN/TaN) as gate material. From the linear dependence of the normalized drain noise on the gate voltage overdrive we conclude that the 1/f noise is dictated by mobility fluctuations. This behavior is mainly ascribed to the reduced mobility ...

We compare the numerical results for electron tunneling currents for single gate oxides, ON-and ONO-structures. We demonstrate that stacked dielectrics can keep the tunneling currents a few orders of magnitude lower than electrostatically equivalent single oxides. We also discuss the impact of gate material and the modeling of electron transport in silicon.

This paper describes a gate-level power minimization methodology using dual supply voltages. Gates and flip-flops off the critical paths are made to operate at the reduced supply voltage to save power. Core technologies are dual-V DD circuit synthesis and P&R. We give a brief overview on existing low-power EDA technologies as background and discuss advantages and challenges of the dual-VDD appr...

A new member of the layered pseudo-1D material family-monoclinic gallium telluride (GaTe)-is synthesized by physical vapor transport on a variety of substrates. The [010] atomic chains and the resulting anisotropic behavior are clearly revealed. The GaTe flakes display multiple sharp photoluminescence emissions in the forbidden gap, which are related to defects localized around selected edges a...

In this paper, we explore the scaling limits of alternative gate dielectrics based on their direct-tunneling characteristics and gate-leakage requirements for future CMOS technology generations. Important material parameters such as the tunneling effective mass are extracted from the direct-tunneling characteristics of several promising highgate dielectrics for the first time. We also introduce...

Molybdenum disulfide (MoS2) has attracted a great attention as an excellent 2D material for future optoelectronic devices. Here, a novel MoS2 tribotronic phototransistor is developed by a conjunction of a MoS2 phototransistor and a triboelectric nanogenerator (TENG) in sliding mode. When an external friction layer produces a relative sliding on the device, the induced positive charges on the ba...