Double-gate fully depleted (DGFD) SOI circuits are regarded as the next generation VLSI circuits. This paper investigates the impact of scaling on the demand and challenges of DGFD SOI circuit design for low power and high performance. We study how the added back-gate capacitance affects circuit power and performance; how to tradeoff the enhanced short-channel effect immunity with the added bac...

Universal multiple-qubit gates can be implemented by a set of universal single-qubit gates and any one kind of entangling two-qubit gate, such as a controlled-NOT gate. For semiconductor quantum dot qubits, two-qubit gate operations have so far only been demonstrated in individual electron spin-based quantum dot systems. Here we demonstrate the conditional rotation of two capacitively coupled c...

With the scaling of MOSFETs in to sub-100nm regim, Silicon – on – Insulator (SOI), single gate (SG) and double gate (DG) MOSFETs are expected to replace tradional bulk MOSFETS. These novel MOSFETs devices will be strong contenders in RF applications in wireless communication market. This work is concerned about the device scaling and different design structures of nano scale SOI MOSFETs. The co...

We report the dispersive readout of the spin state of a double quantum dot formed at the corner states of a silicon nanowire field-effect transistor. Two face-to-face top-gate electrodes allow us to independently tune the charge occupation of the quantum dot system down to the few-electron limit. We measure the charge stability of the double quantum dot in DC transport as well as dispersively v...

The significance of optimization of gate–source/drain extension region (also known as underlap design) in double gate (DG) silicon-on-insulator (SOI) FETs to improve the linearity performance of a low power folded cascode operational transconductance amplifier (OTA) is described. Based on a new figure-of-merit (FoM) involving AV , linearity, fT and dc power consumption PDC , the paper presents ...

High leakage currents and short channel effects become significant enough to be the major concerns for circuit designers as semiconductor devices are miniaturized. Tunnel field effect transistor(TFET) show good scalability and have very low leakage current .These transistors have very low leakage current, good sub-threshold swing, improved short channel characteristics and lesser temperature se...

The paper presents a simulation study of the electrical characteristic of Bulk Planar Junctionless Transistor (BPJLT) using spacer. The BPJLT is a transistor without any PN junctions in the vertical direction. It is a gate controlled variable resistor. The characteristics of BPJLT are analyzed by varying the oxide material under the gate. It can be shown from the simulation that an ideal subthr...

Gwanghyeon Baek (SID Student Member) Jerzy Kanicki (SID Member) Abstract — The equations for the transfer characteristics, subthreshold swing, and saturation voltage of double-gate (DG) a-IGZO TFTs, when the topand bottom-gate electrodes are connected together (synchronized), were developed. From these equations, it is found that synchronized DG a-IGZO TFTs can be considered as conventional TFT...

A key concept in the emerging field of spintronics is the gate voltage or electric field control of spin precession via the effective magnetic field generated by the Rashba spin-orbit interaction. Here, we demonstrate the generation and tuning of electric field induced Rashba spin-orbit interaction in InAs nanowires where a strong electric field is created by either a double gate or a solid ele...

Solution-processed gate dielectrics were fabricated with the combined ZrO2 and Al2O3 (ZAO) in the form of mixed and stacked types for oxide thin film transistors (TFTs). ZAO thin films prepared with double coatings for solid gate dielectrics were characterized by analytical tools. For the first time, the capacitance of the oxide semiconductor was extracted from the capacitance-voltage propertie...