This paper presents the design of low power and high speed circuit using a new CMOS logic family called feedthrough logic. FTL arithmetic circuits provides for smaller propagation time delay when compared with the standard CMOS technologies. The proposed circuit has very low dynamic power consumption and lower propagation delay compared to the recently proposed circuit techniques for the dynami...

An arithmetic circuit or formula is multilinear if the polynomial computed at each of its wires is multilinear. We give an explicit example for a polynomial f(x1, ..., xn), with coefficients in {0, 1}, such that over any field: 1. f can be computed by a polynomial-size multilinear circuit of depth O(log n). 2. Any multilinear formula for f is of size nΩ(logn). This gives a super-polynomial gap ...

We present an efficient addition circuit, borrowing techniques from the classical carry-lookahead arithmetic circuit. Our quantum carrylookahead (qcla) adder accepts two n-bit numbers and adds them in O(log n) depth using O(n) ancillary qubits. We present both in-place and out-of-place versions, as well as versions that add modulo 2n and modulo 2n − 1. Previously, the linear-depth ripple-carry ...

Received Mar 27, 2013 Revised Jun 21, 2013 Accepted Jul 2, 2013 In this paper, we proposed a novel heuristic method based on Imperialist competitive Algorithm (ICA) to design combinational logic modules which performing different arithmetic functions. According to conventional methods, for multi functional circuit, a distinct circuit is designed for each specific function and then all of them a...

Reversible circuit designing is the area where researchers are focussing more and more for the generation of low loss digital system designs. Researchers are using the concept of Reversible Logic in many areas such as Nanotechnology, low loss computing, optical computing, low power CMOS design etc. Here we have proposed a novel design approach for a 2-bit binary Arithmetic Logic Unit (ALU) usin...

Current logic synthesis techniques are ineffective for arithmetic circuits. They perform poorly for XOR-dominated circuits, and those with a high fan-in dependency between inputs and outputs. Multipliers are particularly challenging because of the high fanout that results from the partial product generator. Many optimizers, therefore employ libraries of hand-optimized arithmetic components, but...

We suggest practical sub-linear size zero-knowledge arguments for statements involving linear algebra. Given commitments to matrices over a finite field, we give a sub-linear size zero-knowledge argument that one committed matrix is the product of two other committed matrices. We also offer a sub-linear size zero-knowledge argument for a committed matrix being equal to the Hadamard product of t...

We say that a polynomial f(x1, . . . , xn) is indecomposable if it cannot be written as a product of two polynomials that are defined over disjoint sets of variables. The polynomial decomposition problem is defined to be the task of finding the indecomposable factors of a given polynomial. Note that for multilinear polynomials, factorization is the same as decomposition, as any two different fa...

As the requirement of low power high performance arithmetic circuits, in this paper we introduced a design of new MT-CMOS domino logic and FTL dynamic logic technique to design adder circuit. The MT-MOS transistors reduce the power dissipation by minimizing sub threshold leakage current in domino logic circuits introduced. The MT-NMOS transistor connected in discharging path of output inverter ...

We present work toward the development of a digital to analog (DAC) conversion scheme to efficiently achieve the bit-depths required in high performance infrared scene projection. This is achieved by appropriately dividing the conversion amongst the close support electronics (CSE), the periphery of the read-in integrated-circuit (RIIC) chip, and the pixel drive circuitry.