This chapter introduces the first basic concepts of co-modelling and co-simulation, including notions of system, model and co-model, simulation and co-simulation, etc. It also describes the ways in which co-modelling and co-simulation can be integrated with established development processes such as IEEE 15288 (Systems and Software Engineering—System Life Cycle Processes, [45]) and IEEE 12207 (S...

Instruction set extension (ISE) is an effective approach to improve the processor performance without tremendous modification in its core architecture. To execute ISE(s), a processor core must be augmented with a new functional unit, called application specific functional unit (ASFU), which consists of multiple hardware implementation options of ISEs (ISE_HW). Obviously, since ISE_HW increases ...

Applying system-level fault-tolerant techniques such as active redundancy is a promising way to enhance the system reliability for safety-related applications. Embedded system design using active redundancy is a challenging task that involves solving two major problems, namely finding the optimal redundancy configuration and mapping/scheduling of the application (including the redundant compone...

1 Computing Lower Bounds on Functional Units Before Scheduling1 Samit Chaudhuri2, Robert A. Walker3 Abstract|This paper presents a new polynomial-time algorithm for computing lower bounds on the number of functional units (FUs) of each type required to schedule a data ow graph in a speci ed number of control steps. A formal approach is presented that is guaranteed to nd the tightest possible bo...

reconfiguration (PR) enhances traditional FPGA-based high-performance reconfigurable computing by providing additional benefits such as reduced area and memory requirements, increased performance, and increased functionality. However, since leveraging these additional benefits requires specific designer expertise, which increases design time, PR has not yet gained widespread usage. Even though ...

Software-intensive embedded systems are characterized by an increasing number of features that implement complex safety-critical functionalities. These systems are more and more developed in a model-based fashion that has been considered as a central design approach to deal with the increase in software complexity. These kinds of embedded systems always require multiple constraints both functio...

This survey presents a perspective on the existing research and practices initiated for the Design Space Exploration (DSE) in Multiprocessor System on Chip (MPSoC) technology. Reduction in size as well as adding more functionality within a single chip by incorporating multiple processors remains the key in the development of the modern MPSoC. This rapid development has been made possible becaus...

As we enter the deep submicron era, the number of transistors integrated on die is exponentially increased. While the additional transistors largely boost the processor performance, a repugnant side effect caused by the evolution is the ever-rising power consumption and chip temperature. It is widely acknowledged that the shortage of power supplied to a processor will be a major hazard to susta...

This paper presents a design space exploration method for mixed eventtriggered and time-triggered real-time systems in the automotive domain. A design space exploration model is used that is capable of modeling and optimizing state-ofthe-art automotive systems including the resource allocation, task distribution, message routing, and scheduling. The optimization is based on a heuristic approach...

|This paper presents a new polynomial-time algorithm for computing lower bounds on the number of functional units (FUs) of each type required to schedule a data ow graph in a speci ed number of control steps. A formal approach is presented that is guaranteed to nd the tightest possible bounds that can be found by relaxing either the precedence constraints or integrality constraints on the sched...