A systematic technique for designing a continuous-time sigma-delta modulator @AhI) is presented. The continuous-time m open-loop transfer function is obtained by the pulse-invariant transformation of its discrete-time equivalent. This method results in an inherently stable XAM and does not need any loss factor to make the modulator stable, and so provides the maximum achievable signal-to-noise ...

In this paper a bandpass MASH (multi-stage noise shaping) sigma-delta (RD) modulator is presented. A SNR (signal to noise ratio) of at least 85 dB (equivalent to a resolution of 14 bits) has been achieved over a 5 MHz band around an intermediate frequency (IF) of 20 MHz using a clock frequency of 80 MHz. This performance is obtained using a sixth order bandpass RD modulator followed by a 10 bit...

This paper presents a 71MS/s oversampling D/A converter for DMT-ADSL applications and focuses on the design and performance analysis of the sigma-delta modulator. Design trade-off among the interpolator, current-mode semi-digital FIR filter and analog continuous-time filter has also been discussed. By optimizing the NTF zeros of the 5-th order modulator with an oversampling ratio of 32, the D/A...

This paper presents the design of an image-reject continuous-time (CT) quadrature bandpass (QBP) ∆Σ modulator using a tailored signal-transfer-function (STF) design. The quadrature delta-sigma noise shaping with polyphase filter implementations and strategic IF placement effectively improve image rejection internally. The Fifth-order CT QBP ∆Σ modulator planned for WiMAX and Bluetooth standards...

In this paper we propose a digital background adaptive calibration technique for correcting offset and gain mismatches in multi-path sigma-delta (ZA) modulators. The proposed technique allows us to cancel the spurious tones introduced by offset and gain mismatches among the paths only by processing the digital output, without interfering with the operation of the modulator. This solution is als...

We present a Sigma-Delta modulator designed for ADSL applications in a 0.35μm CMOS pure digital technology. It employs a 4th-order 3-stage cascade architecture including both single-bit and multi-bit quantizers with programmable resolution, which allows us to use only 16 oversampling ratio. Especial emphasis is placed on technology issues, namely: poor analog performance and substrate coupling....

A double-sampling highpass delta-sigma modulator (HPDSM) with inherent frequency translation is presented. The switched-capacitor highpass filter with double-sampling not only minimizes the number of capacitors required in the feedback network but also enables chopper stabilization which makes the modulator immune to 1/f noise and DC offset. A first-order prototype HPDSM with 3bit quantization ...