With the progress of semiconductor process miniaturization, delay degradation by aging increases and threatens reliability fabricated chips. The amount is known to be circuit workload dependent, but previous evaluations are based on simulations, measurement real under realistic has not been reported yet. authors have already proposed a method, which can achieve enough accuracy measure dependent...

This paper presents experimental results from circuits specially implemented to evaluate a new technique for detecting delay faults in scan based designs. The faults are detected by observing circuit outputs at multiple capture intervals, each progressively shorter than the nominal switching delay for the logic block. For this study a simple datapath circuit was designed and fabricated through ...

A new interleaved synchronous mirror delay (SMD) is proposed in order to reduce the circuit size. The conventional interleaved SMD has multiple pairs of forward delay array (FDA) and backward delay array (BDA) in order to reduce the clock skew. The proposed interleaved SMD requires one FDA and one BDA by changing the position of MUX. Simulation results show that about 30% power reduction and 40...

A unified and consistent representation of logic gates at logic and circuit levels is described based on the subcircuit expansion approach. A dynamic-delay model is proposed for gate-level timing simulation, which includes the effects of nonlinear capacitive loading, input transition time, and multiple-input triggering on the delay. It is shown that the approach provides near circuit-level accu...

We investigate two strategies to guarantee temporal correctness of a combinational circuit. We rst propose a new technique to identify and test primitive faults. A primitive fault is a path delay fault that has to be tested to guarantee the performance of the circuit. Primitive faults can consist of single or multiple path delay faults. Testing strategies for single primitive faults exist. In t...