The need for rapid and cost-effective development Intelligent Tutoring Systems with flexible pedagogical approaches has led to a demand for authoring tools. The authoring systems developed to date provide a range of options and flexibility, such as authoring simulations, or authoring tutoring strategies. This paper describes FlexiTrainer, an authoring framework that enables the rapid creation o...

In this paper we present compiler extensions for the Molen programming paradigm, which is a sequential consistency paradigm for programming custom computing machines (CCM). The compiler supports instruction set extensions and register file extensions. Based on pragma annotations in the application code, it identifies the code fragments implemented on the reconfigurable hardware and automaticall...

The OpenFire processor is an simple, open source solution for implementing a MicroBlaze-compliant Application-Specific Instruction-Set Processor (ASIP) on an FPGA. Its small size and adjustable feature set also make it attractive for Single Chip Multiple Processor (SCMP) research. Until now the OpenFire has been dependent upon a host MicroBlaze processor or custom user logic for access to exter...

We propose application specific virtual machines as a method to safely and efficiently program sensor networks. Although sensor networks encompass a wide range of application domains, any given network supports a single one. A VM tailored to a particular deployment can provide retasking flexibility within its application class while keeping programs efficient. We present Maté, an architecture f...

The M•CORE microRISC architecture has been developed to address the growing need for long battery life among today’s portable applications. In this paper, we will present the low-power design techniques and architectural trade-offs made during the development of this processor. Specifically, we will discuss the initial benchmarking, the development of the Instruction Set Architecture (ISA), the...

In this paper, a digital signal processor (DSP) with programmable correlator array architecture is presented for third generation wireless communication system. The programmable correlator array can be reconfigured as a chip match filter, code group detector, scrambling code detector, and RAKE receiver with low power consideration. The architecture and instruction set of the proposed DSP are sp...

To provide flexibility in deploying new protocols and services, general-purpose processing engines are being placed in the datapath of routers. Such network processors are typically simple RISC multiprocessors that perform forwarding and custom application processing of packets. The inherent unpredictability of execution time of arbitrary instruction code poses a significant challenge in provid...

Much of the improvement in computer performance over the last twenty years has come from faster transistors and architectural advances that increase parallelism. Smaller feature sizes have decreased the transistor switching time but at the same time increased the resistance of interconnect wires, resulting in slower signal transmission in on-chip wiring. Since future chips will have more silico...

Power is becoming a critical constraint for designing embedded applications. Current power analysis techniques based on circuit-level or architectural-level simulation are either impractical or inaccurate to estimate the power cost for a given piece of application software. In this paper, an instruction-level power analysis model is developed for an embedded DSP processor based on physical curr...

| This paper presents a fast and eecient algorithm to estimate the area cost of a given RTL datapath. This is achieved by considering the physical length of components (provided by a component library) and connections data (given by the datapath description) within an actual layout model and using analytical formulas in a constructive algorithm. Our layout estimator uses a non-probabilistic bas...