In this paper, we focus on the practical issues of designing e cient complete exchange algorithms on a commodity cluster interconnected by a non-blocking crossbar switch. Four complete exchange algorithms, including, shift exchange, pairwise exchange, group shu e exchange and synchronous shu e exchange algorithms are studied and tested on a cluster platform. These algorithms feature their own c...

Over the past few years, many high performance asynchronous transfer mode (ATM) switches have been proposed. The majority of these switches have high performance but also high hardware complexity. Therefore, there is a need for switch designs with low complexity and high performance. This research proposes three new ATM switches based on the folded hypercube network (FHC). The performance of th...

A bit permutation network is an s-stage interconnection network composed of dn−1 d × d crossbar switches in each stage. This class of networks includes most of the multistage interconnection networks. Recently, Chang et al. [Networks 33 (1999), 261–267] showed that an sstage d-nary bit permutation network N with dn inputs (outputs) can be characterized by an (s − 1)-vector (k1, . . . , ks−1), w...

Atomic switch is a nanoionic-device that controls the diffusion of metal ions/atoms and their reduction/oxidation processes in the switching operation to form/annihilate a conductive path [1-3]. Since metal atoms can provide a highly conductive channel even if their cluster size is in the nanometer scale, atomic switches may enable downscaling to smaller than the 11 nm technology node, which is...

The unifying theme of this thesis is the design of packet schedulers to provide qualityof-service (QoS) guarantees for various networking problem settings. There is a dual emphasis on both theoretical justification and simulation evaluation. We have worked on several widely different problem settings optical networks, input-queued crossbar switches, and CDMA wireless networks and we found that ...

On-chip networks have emerged as a scalable and high-bandwidth communication fabric in many-core processor chips. However, the energy consumption of these networks is becoming comparable to that of computation cores, making further scaling of core counts difficult. This thesis makes several contributions to low-swing signaling circuit design for the energy efficient on-chip networks in two sepa...

Crossbars are frequently used as the switching fabric for highperformance packet switches (1P routers, ATM switches, Ethernet switches). The performance, functionality, and scalability (in terms of line rate andor number of ports) of these switches are directly related to the arbitrationlscheduling algorithm which must retrieve the state information of input queues, compute a (pseudo-) optimum ...

A Hoppeld neural network is presented for scheduling packets in an input-buuered crossbar switch. The controller has a two-dimensional winner-take-all design and is driven by request signals representing the packets stored in the input buuers. Schemes are presented to support multiple priorities of traac by changing the binary request signals to multi-valued signals that vary over a limited ran...

Crossbars are key components of communication switches used to construct multiprocessor interconnection networks. Multi-queue input buffers have been shown to lead to high performance in such networks by allowing packets at an input port to be processed in non-FIFO order. Symmetric crossbar arbiters efficiently resolve conflicting requests in switches with multi-queue input buffers. While these...

Reducing the design complexity of switches is essential for cost reduction and power saving in on-chip networks. In wormhole-switched networks, packets are split into flits which are then admitted into and delivered in the network. When reaching destinations, flits are ejected from the network. Since flit admission, flit delivery and flit ejection interfere with each other directly and indirect...