This paper presents a CNFET (Carbon Nano-tube FET) based MT (Multi-Threshold)-SRAM (Static Random Access Memory) design on the leakage reduction mechanism. A multi-threshold logic is employed for reducing current during read/write operations. Here, technique used to insert high threshold sleep control low circuit. The insertion performed in serial manner. transistors are very useful deriving su...

A CMOS Current/Voltage mode winner-take-all circuit (WTA) with spatial filtering for image processing applications is presented. This WTA circuit has a unique ability of spatial filtering that allows removal of the background from the image and is suitable for integration with CMOS Active Pixel Sensors. In this circuit, image intensity has been chosen for the input saliency map. The removal pro...

This paper presents a new general purpose neuro-fuzzy controller to realize adaptive-network-based fuzzy inference system (ANFIS) architecture. ANFIS which tunes the fuzzy inference system with a back propagation algorithm based on collection of input-output data makes fuzzy system to learn. To implementing this idea we propose several improved CMOS analog circuits, including Gaussian-like memb...

Nanoelectronic molecular and magnetic tunnel junction (MTJ) MRAM crossbar memory systems have the potential to present significant area advantages (4 to 6F(2)) compared to CMOS-based systems. The scalability of these conductivity-switched RAM arrays is examined by establishing criteria for correct functionality based on the readout margin. Using a combined circuit theoretical modelling and simu...

A new charge pump circuit has been proposed to suppress the return-back leakage current without suffering the gate-oxide reliability problem in low-voltage CMOS process. The four-phase clocks were used to control the charge-transfer devices turning on and turning off alternately to suppress the return-back leakage current. A test chip has been implemented in a 65-nm CMOS process to verify the p...

Currents injected by CMOS digital circuit blocks into the power grid and into the substrate of a system-on-a-chip may affect reliability and performance of other sensitive circuit blocks. To verify the correct operation of the system, an upper bound for the spectrum of the noise current has to be provided with respect to all possible transitions of the circuit inputs. The number of input transi...

Short channel MOSFET devices have been fabricated using a commercial 0.25 μm CMOS process and characterized at cryogenic temperatures for further application in hybrid superconductor-CMOS circuits. A 4 K device model has been established through modifying the room temperature CMOS model by taking into account the parameter variation of the discrete MOS devices at cryogenic temperature. We have ...

In this paper a circuit design technique to improve noise tolerant of a new CMOS domino logic family called feedthrough logic is presented. The feedthrough logic improves the performance of arithmetic circuit as compared to static CMOS and domino logic but its noise tolerant is very less. A 2-input NAND gate is designed by the proposed technique. The ANTE (average noise threshold energy) metric...

0038-1101/$ see front matter 2013 Elsevier Ltd. A http://dx.doi.org/10.1016/j.sse.2013.02.017 ⇑ Corresponding author. E-mail addresses: [email protected] (H iue.tuwien.ac.at (T. Windbacher), [email protected] [email protected] (S. Selberherr). As the feature size of CMOS components scales down, the standby power losses due to high leakage currents have become a top concern for moder...

Tunneling-field-effect-transistor (TFET) has emerged as an alternative for conventional CMOS by enabling the supply voltage (VDD) scaling in ultra-low power, energy efficient computing, due to its sub-60 mV/ decade sub-threshold slope (SS). Given its unique device characteristics such as the asymmetrical source/drain design induced uni-directional conduction, enhanced on-state Miller capacitanc...