The proposed design of HDB3 decoding system using FPGA implementation offers an efficient and unfailing decoding at receiving end by sustaining clock data recovery using Direct Digital Synthesis (DDS). The system captures E1/T1 HDB3 encoded tertiary level stream at input, converts it into binary level symbols, FPGA IO reconcilable, and decode and transforms it into synchronized NRZ output. The ...

A half-rate reference-less clock and data recovery circuit is proposed, incorporating a coarse frequency-locked loop and a fine phase-locked loop with smooth switching to prevent adverse interaction and false locking. Fabricated in a 0.18-μm CMOS process, the recovered clock exhibits a peak-topeak jitter of 60ps for a 2-Gb/s PRBS-7 data and a phase noise of –93.5 dBc/Hz at 1-MHz offset. The cor...

In this paper a CMOS PLL circuit realised for clock and data recovery in interconnection systems is presented. The purpose of this clock recovery PLL is to generate a clock with frequency and phase locked to the input NRZ data, in order to sample them in the optimum point. The topology of the circuit is characterised by two loops, one for the phase lock, the second for a frequency aided acquisi...

The power consumption of the clock tree dominates over 40% of the total power in high performance VLSI designs. Hence, low power clocking schemes are promising approaches for low power design. We propose energy recovery clocked flip-flops that enable energy recovery from the clock network, resulting in significant energy savings. These flip-flops operate with a single-phase sinusoidal clock whi...