It has been a common practice in recent publications concerned with fault tolerance in VLSI and WSI to assume that interconnection buses can be designed to be almost defect-free by enlarging the width of the lines and the spacing between lines. Although this assumption may be valid in many cases, the cost-effectiveness of this proposed “robust” bus layout is questionable especially in the case ...

The paper presents the design and implementation of LVDS (low-voltage differential signaling) receiver circuit, fully compatible with LVDS standard. The proposed circuit is composed of the telescopic amplifier and the comparator with internal hysteresis. The receiver supports 3.5 Gbps data rate with 7.4 mA current at 1.8 V supply according to post-layout circuit simulations. The circuit has the...

A voltage controlled nano addressing circuit is proposed, which (1) improves yield and enables aggressive scaling with no requirement of precise layout design, (2) achieves precision of addressing by transistor current-to-voltage sensitivity in the circuit and applied external address voltages, and (3) is adaptive to and more robust in the presence of process variations which are expected to be...

This tutorial paper reviews the state of knowledge of on-chip ESD (electrostatic discharging) protection circuit design for integrated circuits. The discussion covers critical issues in ESD design, such as, ESD test models, ESD failure mechanism, ESD protection structures, ESD device modeling, ESD simulation, ESD layout issues, and ESD influences on circuit functionality, etc. This review serve...

Superconducting Single-Flux-Quantum (SFQ) devices have been paid much attention as alternative devices for digital circuits, because of their high switching speed and low power consumption. For large-scale circuit design, the role of computer-aided design environment is significant. As the characteristics of the SFQ devices are different from conventional devices, a new design environment is re...

This paper presents a voltage based CMOS winner-take-all (WTA) circuit for analog voltage signals. The WTA circuit is based on a winner follower and wide-range transconductance amplifiers. The voltage based design uses capacitive storage for low power consumption. The circuit is modularized and its layout size is a linear function of the number of inputs. This makes the circuit easy to be imple...

Absfrncr -The computer-aided design of a VLSI PCM-FDM transmultiplexer is presented. The entire design process from sysrem specifiearions to integrated circuit layout is carried out with the aid of specialized computer programs for analysis, synthesis and optimization at each design level: the firter network, the architecture and the circuit layout. These CAD tools support a top-down custom des...

In this paper, we introduce a structural metric, logic contraction, for pre-layout physical connectivity prediction. For a given set of nodes forming a cluster in a netlist, we can predict their proximity in the final layout. We demonstrate experimentally a very good correlation of our pre-layout measure with the post layout physical distances between those nodes. We show an application of the ...

Brain function relies on specificity of synaptic connectivity patterns among different classes of neurons. Yet, the substrates of specificity in complex neuropil remain largely unknown. We search for imprints of specificity in the layout of axonal and dendritic arbors from the rat neocortex. An analysis of 3D reconstructions of pairs consisting of pyramidal cells (PCs) and GABAergic interneuron...

Applications of MEMS variable capacitive sensors are introduced. The design trade-offs of variable capacitive sense amplifiers are discussed and a chopper stabilized variable capacitive sense amplifier topology is introduced. The chopper stabilized topology has the advantage of not being sensitive to 1/f noise, charge injection noise, kT/C noise, and dc offsets. This circuit was designed to mee...