Adders are one of the widely used digital components in digital integrated circuit design. The Carry Select Adder (CSA) provides a good compromise between cost and performance in carry propagation adder design. However, conventional CSA is still area-consuming due to the dual ripple carry adder (RCA) structure. In this paper, modification is done at gate-level to reduce area and power consumpti...

RÉSUMÉ. Dans le cadre du problème de satisfaction de contraintes, nous proposons un nouveau schéma de recherche parallèle coopérative. La coopération est réalisée en échangeant des nogoods (instanciations qui ne peuvent être étendues en une solution). Nous associons un processus à chaque solveur et nous introduisons un gestionnaire de nogoods, afin de réguler les échanges de nogoods. Chaque sol...

In various telecommunication applications Digital Signal Processors are the key components in transferring the data between devices. The implementation of FIR filter on FPGA is based conventional methods increasing the need for considerable hardware resources, which in turn raises the circuit size and lowers the system speed. Most important operation performed in digital signal processing is Mu...

Software-Produktlinien-Entwicklung bietet eine systematische Wiederverwendung von Software-Artefakten. Auf Grund der Tatsache, dass viele Produkte aus einer Produktlinie abgeleitet werden können, ist es unerlässlich Testverfahren zu entwickeln, die zum einen eine möglichst vollständige Abdeckung von allen möglichen Produkten sicherstellen und zum anderen weniger aufwändig sind, als jedes Produk...

Parallel-prefix adders (also known as carry tree adders) are known to have the best performance in VLSI designs. However, this performance advantage does not translate directly into FPGA implementations due to constraints on logic block configurations and routing overhead. This paper investigates three types of carry-tree adders (the Kogge-Stone, sparse Kogge-Stone, and spanning tree adder) and...

Reversible logic circuits have the ability to produce zero power dissipation which has found its importance in quantum computing, optical computing and low power digital circuits. The study presents improved and efficient reversible logic circuits for carry skip adder and carry skip BCD adder. The performance of the proposed architecture is better than the existing works in terms of gate count,...

We compare two 16 bit adders based on the Manchester Carry Chain (MCC) circuit topology using the TSMC .25 µm process technology. The first circuit is a synchronous 16 bit adder based on an optimized 4-bit MCC where the carry out of each of the 4-bit MCCs are ripple carried into the next MCC block through an edge sensitive D-Flip Flop. The second circuit is an asynchronous adder, which uses the...

Application of logical effort on transistor-level analysis of different 64-bit adder topologies is presented. Logical effort method is used to estimate delay and impact of different adder topologies and to evaluate the validity of the results obtained using logical effort methodology. The tested adder topologies were Carry-Select, Han-Carlson, Kogge-Stone, Ling, and Carry-Lookahead adder. The q...

A search algorithm based on non-binary forward checking (nFC) is used to solve the car-sequencing problem. The choice of value ordering heuristics having a dramatic effect on solution time for this problem, different ordering heuristics were implementented. The results obtained by using these methods are compared on the instances reported in the CSPLib.