Despite all of the advantages that circular BIST ofsers compared to conventional BIST approaches in terms of low area overhead, simple control logic, and easy insertion, it has seen limited use because it does not reliably provide high fault coverage. This paper presents a systematic approach for achieving high fault coverage with circular BIST. The basic idea is to add a small amount of logic ...

A new microcode-based BIST(Built-In Self Test) circuitry for embedded memory components is proposed in this paper. The memory BIST implements march algorithms which are slightly modified by adopting DOF(Degree of Freedom) concept to detect ADOFs(Address Decoder Open Faults) on top of conventional stuck faults. Furthermore it is shown that the march BIST modified can capture a few NPSFs(Neighbor...

Recently, a new type of Design-for-Delay-Testability (DfDT) structure and associated Built-In Self-Test architecture for detecting delay faults in digital highperformance circuits has been proposed. It circumvents the requirement of an expensive high-speed tester. In this paper, the ability of the proposed structure to function correctly in an environment with processand application-induced var...

Built-in self-test test registers must segment a circuit such that there exists a feasible test schedule. If a register transfer description is used for selecting the positions of test registers, the space for optimizations is small. In this paper, 1-bit test cells are inserted at gate level, and an initial test schedule is constructed. Based on the information of this schedule, test cells that...

The combination of higher quality requirements and sensitivity of high performance circuits to delay defects has led to an increasing emphasis on delay testing of VLSI circuits. In this context, it has been proven that Single Input Change (SIC) test sequences are more effective than classical Multiple Input Change (MIC) test sequences when a high robust delay fault coverage is targeted. In this...

A complex SoC typically consists of numerous of memories in today's digital systems. This paper presents a test/ repair flow based on memory grouping strategy and a revised distributed BIST structure for complex SoC devices. A gated selecting method is added to the distributed BIST structure. Also, this paper for the first time proposes a robust post repair stage based on BIRA and memory groupi...

A new method of test-per-clock BIST design for combinational circuits is proposed. The fundamental problem of matching the PRPG outputs with the required test patterns is solved as a general design problem in the field of combinational logic. A test set generated by an ATPG is compared with the PRPG generated sequence. The solution is based on a novel search algorithm, which identifies the best...

In this paper a novel architecture for scan-based mixed mode BIST is presented. To reduce the storage requirements for the deterministic patterns it relies on a two-dimensional compression scheme, which combines the advantages of known vertical and horizontal compression techniques. To reduce both the number of patterns to be stored and the number of bits to be stored for each pattern, determin...

Core reuse is an emerging IC design style which enables rapid development of highly complex ICs. Reusable circuit cores come in two basic varieties, hard and soft. Hard cores are optimized for area and performance and are not modifiable by the user, whereas soft cores are user modifiable. If soft cores do not contain testability (i.e. scan/BIST), it can be inserted into the core by the user. Ha...