This paper presents a technique for nding good distributions of arrays and suitable loop restructuring transformations so that communication is minimized in the execution of nested loops on message passing machines. For each possible distribution (by one or more dimensions), we derive the best unimodular loop transformation that results in block transfers of data. Unlike other work which focus ...

The aim is to present a new data distribution of triangular matrices that provides steady distribution of blocks among processes and reduces memory wasting compared to the standard block-cyclic data layout used in the ScaLAPACK library for dense matrix computations. A new algorithm for solving triangular systems of linear equations is also introduced. The results of experiments performed on a c...

a facility layout problem is concerned with determining the best position of departments, cells, or machines on the plant. an efficient layout contributes to the overall efficiency of operations. it’s been proved that, when system characteristics change, it can cause a significant increase in material handling cost. consequently, the efficiency of the current layout decreases or is lost and it ...

Metal-based additive manufacturing processes require a supporting of overhanging part areas during the powder solidification e. g. for improving the heat dissipation to the substrate. Technology users nowadays strive to reduce support areas due to economical aspects, while simultaneously enhancing the process stability by maximizing the support stiffness. For the simplification and acceleration...

In this paper, the design considerations of a mixed-signal integrated circuit for a 2D matrix ultrasonic transducer will be presented. The IC and the matrix transducer will be put into the tip of a transesophageal (TEE) probe for 3D echocardiography. The challenges associated with the interface electronics include: addressing the huge amount of elements, do the beam steering in the transmission...

This paper presents the design pow for a Superscalar VLIWmicroprocessorusing the 0.8 p CMOS portable ASIC library developed in the framework of the ESPRIT2 IDPS project. A ful l set of cell libraries and macro-block generators have been used, in order to achieve fast design cycle, and still maintains a high level of integration and performance. The final circuit contains about875 000 transistor...

This paper proposes an effective fingerprint identification system with hardware block for thinning stage processing of a verification algorithm based on minutiae with 39% occupation of 32-bit RISC microprocessor cycle. Each step of a fingerprint algorithm is analyzed based on FPGA and ARMulator. This paper designs an effective hardware scheme for thinning stage processing using the Verilog-HDL...

In this paper, we present and analyze yield enhancement designs for wafer scale Cube Connected Cycles (CCC). Improvements in yield can be achieved through silicon area reduction and/or through the incorporation of defect/fault tolerance into the architecture. Consequently, we first propose a new compact layout strategy for CCC. We then present a novel implementation of wafer scale CCC based on ...

A 150 GHz amplifier in digital 65 nm CMOS process is presented. Matching loss is reduced and bandwidth extended by simplistic topology: no dc-block capacitor, shunt-only tuning and radial stubs for ac ground. Dummy-prefilled microstrip lines, with explicit yet efficient dummy modeling, are used as a compact, density-rule compliant matching element. Transistor layout with parallel gate feed yiel...

Understanding a block of handwritten text means mapping it into a semantic representation, We describe an approach to reading a I>lock of handwritten text when there arc certain loose constraints placed on the spatial layout and syntax 01 the tnt. Early recognition of primitives guides the location of syntactic components. A system to read handwritten postal addresses is described as an instanc...