Abstract—This paper is the second in a series of two papers describing the methodology and algorithms used in the development of MISTIC (Michigan Synthesis Tools for Integrated Circuits). Part I discussed the basic topological algorithms used to produce generic sequences of processing steps required for the fabrication of a given device structure. Part II discusses the expansion of these sequen...

In this paper, we describe how we have exploited the advantages of various methods for device recognition and modeling in a layout-to-circuit extractor, called Space. Hence, we have obtained a program that, for different technologies, can quickly translate a large layout into an equivalent network. The network includes layout parasitics of the interconnects and can directly be simulated by vari...

We demonstrate an 850-nm high-speed photoreceiver with a monolithically integrated silicon avalanche photodetector for optical interconnect applications. The photoreceiver is fabricated with standard 0.25-μm SiGe bipolar complementary metal-oxide-semiconductor technology without any process modification. The photoreceiver achieves 7-Gb/s optical data transmission with the bit-error rate less th...

In this paper, the design requirements of different mixers for direct conversion receivers are discussed. Special attention has been paid into the detection of amplitude-modulated RF signal envelope. Three active mixers have been implemented to investigate the discussed requirements by using a 0.35-μm, 25-GHz BiCMOS technology. The same process allows an objective comparison between the differe...

With the growing interest and the emergence of various implementations of MultipleValued logic (MVL) circuits, testability issues of these circuits are becoming crucial. Fault characterization is an early step in the test generation process. It is aimed at finding fault models that best describe the possible faults expected to occur in a given class of circuits or technology. Layout and device ...