Home networking has been developing rapidly due to the increase of the internet users and the advent of digital economy. In this context, the quality and service under guarantee for internet intelligence electric home appliances has become quite important. Therefore, to guarantee the performance of the appliances, on-line testing for detecting latency faults should be performed. In this paper, ...

3⁄4 In order to accomplish a high speed test on low speed Automatic Test Equipment (ATE), a new instruction based, fully programmable memory, Built-in Self-Test (BIST) is proposed. The proposed memory BIST generates a high speed internal clock signal by multiplying the external low speed clock signal from the ATE. For maximum programmability and small area overhead, the proposed BIST receives t...

This paper proposes a histogram BIST scheme for ADC static testing. This scheme makes use of time decomposition technique and space decomposition technique. The traditional ADC BIST approach based on time decomposition technique can reduce the test hardware overhead, however it will typically produce large testing time. For a monotonic ADC, the output codes have an approximate proportional rela...

We present a new pseudorandom testing algorithm f o r the Built-In Self-Test (BIST) of DRAM. In this algorithm, test patterns are complemented to generate state-transitions that are needed f o r the detection of coulping faults. A s a result, the number of test patterns required is less than half of the traditional method, while the extra hardware is negligible.

The issue of SOC testing is one of the most crucial in their design and production process. A popular solution for SOCs including microprocessor cores is based on letting them execute a test program, thus implementing a very attracting BIST solution. This paper describes a method for the generation of effective programs for the self-test of a processor starting from its RT-level description. Th...

Formulation of closed form expressions for computingMISR aliasing probability exactly had remained an unsolved problem.This paper presents single and multiple MISR aliasing probability expres-sions for arbitrary test lengths. A framework, based on algebraic codes,is developed for the analysis and synthesis of MISR-based test responsecompressors for BIST. This framework is us...

A new test pattern generator to reduce the number of transition at scan input during scan shifting is proposed. The method is based on generating more correlative neighboring bits by interchanging adjacent bits in a test pattern. The proposed work is known as Bit Interchanging Teat Pattern Generator (BI-TPG) and it consists of basic XOR, XNOR, AND gates, 2:1 Multiplexer and a register. The leng...

We present design of a two-dimensional (2-D) discrete cosine transform (DCT) circuit with built-in self-test (BIST) capability. After modifying an existing fast 2-D DCT algorithm to make it more flexible, we synthesized the data path and the controller using our high-level BIST synthesis tool and incorporated scan design to other modules. Our design achieves high fault coverage at small cost of...

© 2013 ETRI Journal, Volume 35, Number 5, October 2013 Programmable memory built-in self-test (PMBIST) is an attractive approach for testing embedded memory. However, the main difficulties of the previous works are the large area overhead and low flexibility. To overcome these problems, a new flexible PMBIST (FPMBIST) architecture that can test both single-port memory and dual-port memory using...

This paper presents a novel approach for test generation and test scheduling for multi-clock domain SoCs. A concurrent hybrid BIST architecture is proposed for testing cores. Furthermore, a heuristic for selecting cores to be tested concurrently and order of applying test patterns is proposed. Experimental results show that the proposed heuristics give us an optimized method for multi clock dom...