Sleep-wake scheduling (or duty cycling) of radio transceivers is a well known technique for achieving energy conservation in wireless ad hoc and sensor networks. While putting nodes to sleep for certain durations of time saves energy since they cannot transmit, receive or listen, it also results in lower throughput capacity in the network and increased packet latency. At low rates of duty cycli...

Introduction Long Latency Auditory Evoked Potentials (LLAEP) with speech sounds has been the subject of research, as these stimuli would be ideal to check individualś detection and discrimination. Objective The objective of this study is to compare and describe the values of latency and amplitude of cortical potentials for speech stimuli in adults with normal hearing. Methods The sample populat...

Recent advances in animal welfare science used judgement bias, a type of cognitive bias, as a means to objectively measure an animal's affective state. It is postulated that animals showing heightened expectation of positive outcomes may be categorised optimistic, while those showing heightened expectations of negative outcomes may be considered pessimistic. This study pioneers the use of a por...

OBJECTIVE To evaluate intra-tester reliability of P300 more precisely, this study was designed. Event-related potential (ERP) is the result of endogenous brain response following cognitive stimulus. The P300 component of the human ERP is a positive wave with a latency of 300 ms or greater. Our purpose of this study was to estimate reliability of P300 latency and amplitude with 30 normal persons...

Low latency is a critical requirement in some switching applications, specifically in parallel computer interconnection networks. The minimum latency in switches with centralized arbitration comprises two components, namely, the control-path latency and the data-path latency, which in a practical high-capacity, distributed switch implementation can be far greater than the cell duration. We intr...

This paper analyzes the design trade-offs in architecting large-scale DRAM caches. Prior research, including the recent work from Loh and Hill, have organized DRAM caches similar to conventional caches. In this paper, we contend that some of the basic design decisions typically made for conventional caches (such as serialization of tag and data access, large associativity, and update of replace...

Photonic networks-on-chip based on silicon photonics have been proposed to reduce latency and power consumption in future chip multi-core processors (CMP). However, high performance CMPs use a shared memory model which generates large numbers of short messages, creating high arbitration latency overhead for photonic switching networks. In this paper we explore techniques which intelligently use...

OBJECTIVES P1 is a robust positivity at a latency of 50-150 msec in the auditory evoked potential of young children. It has been reported that over the first 2-3 years of life, there is a rapid decrease of the latency and the mean P1 latency in adults with normal hearing is approximately 60 msec. This study was designed to evaluate the change of the P1 latency in Koreans with normal hearing acc...

BACKGROUND Middle and late latency auditory evoked potentials. AIM to verify the occurrence of middle and late latency auditory evoked potentials disorders in adults with Acquired Immunodeficiency Syndrome (AIDS). METHOD Middle and late latency auditory evoked potentials of 8 individuals with AIDS, with ages ranging from 10 to 51 years, with normal hearing, or with sensoryneural hearing los...