Memory elements play a vital role on Digital World. In memory devices the most important factor is power consumption. Because the power consumption of the memory device increases means, the device reliability and life time is reduced. The basic memory elements of designer considerations are Latch and Flip-flop. In this paper we design SRAM using arrays of flip-flops and we analyze the design of...

Flip-flops are critical timing elements in digital circuits which have a large impact on circuit speed and power consumption in VLSI circuits. In this paper, a dualedge triggered flip-flop with high performance and clock gated sense amplifier flip-flop is designed. Moreover, the pulse generator can be shared among many flip-flops to reduce the power dissipation and chip area. By incorporating t...

The dynamic behavior of surface dimers on Ge(001) has been studied by positioning the tip of a scanning tunneling microscope over single flip-flopping dimers and measuring the tunneling current as a function of time. We observe that not just symmetric, but also asymmetric appearing dimers exhibit flip-flop motion. The dynamics of flip-flopping dimers can be used to sensitively gauge the local p...

This paper describes a high-speed GaAs MESFET digital IC design for optical communication systems. We propose novel circuit configurations of a selector and a static delayed flip-flop which are key elements to perform high-speed digital functions. Employing these new design, the selector IC and static decision IC fabricated with 0.12-μm GaAs MESFET operated up to 44 Gbit/s and 22 Gbit/s, respec...

QCA (Quantum Dot Cellular Automata) is an emerging and pioneer technology, which is a paradigm for computing with interacting quantum dots. Many eminent researchers have well thought of eloquent work in the existing areas of the sequential circuit. However, this paper proclaims three new approaches to design JK and T flip-flop. Since flip-flops and memory design are the crucial building blocks ...

[Pram90] A. Pramanick, S. Reddy, " On the design of path delay fault testable combinational circuits " , Proc. at time t. After the application of the next clock the contents of the even flip-flops of the LFSR are shifted into the odd ones (see Figure 10b) producing the second vector. The content of the first output is derived by XORing the outputs of some flip-flops including the last one. Not...

Abstract— the objective to design and compare a low-power flip-flop (FF) design presenting an explicit type pulsetriggered framework. Pulse triggered method use used for clock to resolves lengthy discharging path issue in conventional explicit type pulse-triggered FF (P-FF) design and achieves better rate and energy efficiency. A novel power effective pulse triggered flip-flop design with lowes...

The development of a practical magnetic tunneling junction (MTJ) ten years ago allowed the creation of a new class of non-volatile memories. This technology may offer superior resistance to total ionizing dose and virtually unlimited write endurance, making it more attractive than flash memories for space applications. Although a number of manufacturers are developing high-density bulk magnetic...