In Present scenario battery-powered hand-held multimedia systems become popular. The power consumption in these devices is a major concern these days for its long operational life. Although various techniques to reduce the power dissipation has been developed. The most adopted method is to lower the supply voltage. But lowering the Vdd reduces the gate current much more rapidly than the sub-thr...

Problem statement: As technology scales down, the integration density of transistors increases and most of the power is dissipated as leakage. Leakage power reduction is achieved in Static Random Access Memory (SRAM) cells by increasing the source voltage (source biasing) of the SRAM array. Another promising issue in nanoscaled devices is the process parameter variations. Due to these variation...

In this paper we propose a novel design of a low power static random access memory (SRAM) cell for high-speed operations. The model adopts the voltage mode method for reducing the voltage swing during the write operation switching activity. Dynamic power dissipation increases when the operating frequency of the SRAM cell increases. In the proposed design we use two voltage sources connected wit...

Carbon nanotube field-effect transistor (CNTFET) refers to a field-effect transistor that utilizes a single carbon nanotube or an array of carbon nanotubes as the channel material instead of bulk silicon in the traditional MOSFET structure. Since it was first demonstrated in 1998, there have been tremendous developments in CNTFETs, which promise for an alternative material to replace silicon in...

Scaling of SRAM cell beyond 65-nm poses a serious threat to the stability of the cell and is a cause of major concern for the upcoming technologies. Due to random dopant fluctuation (RDF) and other process parameter variations, the cell turns out to be unstable. In this paper, an 8T (8Transistor) SRAM cell is proposed which offers enhanced data stability during read operation. While reading, th...

In nanometer scale static-RAM (SRAM) arrays, systematic inter-die and random within-die variations in process parameters can cause significant parametric failures, severely degrading parametric yield. In this paper, we investigate the interaction between the inter-die and intra-die variations on SRAM read and write failures. To improve the robustness of the SRAM cell, we propose closed-loop ada...

On chip cache memories contributes a large fraction to the total power consumption of microprocessor. As technology scales down into d e e p -submicron, leakage power is becoming a dominant source of power consumption. As cache memory is an array structure leakage reduction in just one memory cell can on the whole reduce a large amount of leakage power. In this thesis leakage power of conventio...

Spin-Transfer Torque Magnetoresistive RAM (STTMRAM) is being intensively explored as a promising on-chip last-level cache (LLC) replacement for SRAM, thanks to its low leakage power and high storage capacity. However, the write penalties imposed by STT-MRAM challenges its incarnation as a successful LLC by deteriorating its performance and energy efficiency. This write performance characteristi...

Recent advances in the development of image watermarking algorithms had made a rapid change in the authenticated information resource sharing. Among all techniques of image watermarking and storing watermarked image bits in SRAM (Static Random Access Memory), LFSR (Linear Feedback Shift Register) based image watermarking technique has been proposed in [1], this technique utilizes less design co...