Lower/Upper triangular (LU) factorization plays an important role in scientific and high performance computing. This paper presents an implementation of the LU decomposition algorithm for double precision complex numbers on a star topology based multi-FPGA platform. The out of core implementation moves data through multiple levels of a hierarchical memory system (hard disk, DDR SDRAMs and FPGA ...

Manipulating configurable resources like FPGAs in a codesign framework has become essential: especially, FPGAs may efficiently implement parallel systematic signal processing tasks. Nevertheless, such implementations are usually hand written at a low level. Our proposition is to provide high level modeling of an application and tools to automatically generate tuned VHDL code from these high lev...

Field-programmable gate arrays (FPGAs) are excellent devices for high-performance computing, system-on-chip realization, and rapid system prototyping. While FPGAs offer flexibility and performance, they continue to lag behind application specific integrated circuit (ASIC) performance and power consumption. As manufacturing technology improves and IC feature size decreases, FPGAs may further lag...

This paper describes design decisions for JOP, a Java Optimized Processor, implemented in an FPGA. FPGA density-price relationship makes it now possible to consider them not only for prototyping of processor designs but also as final implementation technology. However, using an FPGA as target platform for a processor different constraints influence the CPU architecture. Digital building blocks ...

FPGAs are well accepted as an alternative to ASICs and for rapid prototyping purposes. Netlists of designs which are too large to be implemented on a single FPGA, have to be mapped onto a set of FPGAs, which could be organized on an FPGA board containing various FPGAs connected by interconnection networks. This paper presents an efficient approach to the problem of multiway partitioning of larg...

Striped FPGA [1], or pipeline-recon gurable FPGA provides hardware virtualization by supporting fast run-time recon guration. In this paper we show that the performance of striped FPGA depends on the recon guration pattern, the run time scheduling of con gurations through the FPGA. We study two main con guration scheduling approachesCon guration Caching and Data Caching. We present the quantita...

This paper compares selected digital signal processing algorithms on a variety of computing platforms in terms of achievable performance and cost. The experiments were carried out on a standard PC platform, DSP, a RISC microcontroller and on Xilinx XC4013XL FPGA. Our results confirm that general purpose microprocessors are not well suited to these tasks. Both DSP and FPGA achieve higher perform...

This paper presents the HW/SW co-design of a reconfigurable IP video surveillance and control system based on low cost Xilinx Spartan 3E FPGA family. The system allows users to observe video images captured by a camera via any standard browser and control remote devices. Our design focuses on the design of the HW base line JPEG encoder on FPGA and the design of a SW web server running on uCLinu...

SUMMARY A processing system with multiple field programmable gate array (FPGA) cards is described. Each FPGA card can interconnect using six I/O (up, down, left, right, front, and back) terminals. The communication network among FPGAs is scalable according to user design. When the system operates multi-dimensional applications, transmission efficiency among FPGA improved through user-adjusted d...

FPGAs have become quite popular for implementing digital circuits and systems because of reduced costs and fast design cycles. This has led to increased complexity of FPGAs, and with technology scaling, many new challenges have come up for the FPGA industry, leakage power being one of the key challenges. The current generation FPGAs are being implemented in 90nm technology, therefore, managing ...