With the increase in the complexity of digital VLSI circuit design, logic design errors can occur during synthesis. In this work, we present a test vector simulation based approach for multiple design error diagnosis and correction. Diagnosis is performed through an implicit enumeration of the erroneous lines in an effort to avoid the exponential explosion of the error space as the number of er...

Low power has emerged as a principal theme in today’s world of electronics industries. Power dissipation has become an important consideration as performance and area for VLSI Chip design. With shrinking technology reducing power consumption and over all power management on chip are the key challenges below 100nm due to increased complexity. For many designs, optimization of power is important ...

This work presents a methodology to analyze aging effects in different flip-flops topologies. As CMOS transistor scaling to nanometer technologies in the last decades, new issues have become major concerns in VLSI design. One of those new issues is aging. Aging effects impact on performance and reliability of CMOS circuits. Flip-flops are one of the main structures in VLSI circuits. Their chara...

With the increasing complexity of VLSI circuits, simulation of digital circuits is becoming a more complex and time-consuming task. General purpose parallel processing machines are increasingly being used to speed up a variety of VLSI CAD applications. All previous works on mapping sequential logic simulation algorithms onto general purpose parallel machines were centered around using Event-Dri...

We use constrained optimization to select operating parameters for two circuits: a simple 3-transistor square root circuit, and an analog VLSI artificial cochlea. This automated method uses computer controlled measurement and test equipment to choose chip parameters which minimize the difference between the actual circuit's behavior and a specified goal behavior. Choosing the proper circuit par...

Input vector control is an effective technique for reducing the leakage current of combinational VLSI circuits when these circuits are in the sleep mode. In this paper a design technique for applying the minimum leakage input to a sequential circuit is proposed. Our method uses the built-in scan-chain in a VLSI circuit to drive it with the minimum leakage vector when it enters the sleep mode. U...

As technology advances to giga-scale integration level, global interconnect resource becomes increasingly valuable in a VLSI chip. This is due to the exponential growth of the total number of interconnects/wires as the feature size of MOS transistors decreases in scaled deep submicron CMOS technologies. Interconnect length, however, has not scaled down with feature size and remains long relativ...

Power dissipation has emerged as an important design parameter in the design of microelectronic circuits, especially in portable computing and personal communication applications. In this paper, we survey state-of-the-art optimization methods that target low power dissipation in VLSI circuits. Optimizations at the circuit, logic, architectural and system levels are considered.

Power dissipation is an increasing concern in VLSI circuits. New logic circuits have been developed to meet these power requirements. Power dissipation can be minimized by using various adiabatic logic circuits. In this paper an Adder circuit has been proposed based on 2PASCL and ECRL logic and then compared with Positive Feedback Adiabatic Logic(PFAL), Two-Phase Adiabatic Static Clocked Logic(...

In this paper, we propose an approach to design and implementation of VLSI circuits free of electrical supply and power rails. With this approach, the circuits can be made to use the power carried by the incident light for supply, control, and optical charge pumping. The circuits can be fabricated in a standard CMOS technology without additional process. A test circuit involving basic gates and...