In this paper, we propose a fully-utilized, block-based 2D DWT (discrete wavelet transform) architecture, which consists of four 1D DWT filters with two-channel QMF lattice structure. The proposed architecture requires about 2MN-3N registers to save the intermediate results for higher level decomposition, where M and N stand for the filter length and the row width of the image respectively. Fur...

VLSI implementation complexities of soft-input soft-output (SISO) decoders are discussed. These decoders are used in iterative algorithms based on Turbo codes or Low Density Parity Check (LDPC) codes, and promise significant bit error performance advantage over conventionally used partial-response maximum likelihood (PRML) systems, at the expense of increased complexity. This paper analyzes the...

Among the biometric modalities suitable for mobile applications, face verification is definitely an interesting one, because of its low level of invasiveness, and because it is easily applicable from the user viewpoint. Additionally, a reduced cost of the identity verification device is possible when sharing the imaging device between different applications. This is for instance not possible wi...

This paper presents VLSI/WSI designs for a recently introduced parallel architecture known as the folded cube-connected cycles ( F C C C ) . We first discuss two layouts for the FCCC, in which there is no component redundancy. Then we incorporate redundancy, and present locally and globally reconfigurable FCCCs. We also discuss the design of universal building blocks for the construction of fau...

This paper proposes a low-power systolic array architecture for a block-matching motion estimation processor IP for portable and high-resolution video applications. The architecture features a ringconnected processing element (PE) array to reduce both computation cycles and memory access cycles at the same time, allowing lower power characteristics. The feature of low memory access cycles allow...

A new class of FIR ltering algorithms and VLSI architectures based on the multirate approach were recently proposed. They not only reduce the computational complexity in FIR ltering, but also retain attractive implementationrelated properties such as regularity and multiply-and-accumulate (MAC) structure. In addition, the multirate feature can be applied to low-power/high-speed VLSI implementat...

The discrete multitone @MT) modulation/demodulation scheme is the standard transmission technique in the application of asymmetric digital subscriber lines (ADSL). Although the DMT can achieve higher data rate compared with other modulation/ demodulation schemes, its computational complexity is too high for cost-efficient implementations. For example, it requires 512. point IFFUFIT as the modul...

An unified array architecture is described for computation of DFT, DHT, DCT and DST using a modified CORDIC (CoOrdinate Rotation DIgital Computer) arithmetic unit as the basic Processing Element (PE). All these four transforms can be computed by simple rearrangement of input samples. Compared to five other existing architectures, this one has the advantage in speed in terms of latency and throu...

Reconfigurablele optical interconnects enable flexible and high-performance communication in multi-chip architectures to be arbitrarily adapted, leading to efficient parallel signal processing. The use of Opto-VLSI processors as beam steerers and multicasters for reconfigurable inter-chip optical interconnection is discussed. We demonstrate, as proof-of-concept, 2.5 Gbps reconfigurable optical ...

Semi-parallel architectures for decoding Digital Video Broadcasting-Satellite 2 (DVB-S2) Low-Density Parity-Check (LDPC) codes have improved Very Large Scale Integration (VLSI) solutions, but their design is challenging from several perspectives. In order to conveniently exploit parallelism for obtaining VLSI LDPC decoders that occupy small circuit areas and demand low power consumption, we pro...