Our group has created a dynamically translating VLIW processor that uses firmware for instruction scheduling. The processor executes MIPS instructions by dynamically translating them into VLIW, and then executing the translated code. We have also implemented a combined toolchain that compiles C to binary for our VHDL processor. The motivation behind the project was to gain practice writing an a...

This paper introduces the mapping of MPEG video decoders on ADRES, IMEC’s new coarse-grain reconfigurable and fully C-programmable array processor that targets nomadic devices. ADRES is a flexible template that allows the instantiation of many different processor versions. An XML-based architecture description language allows a designer to easily generate different processor instances with full...

© Copyright Hewlett-Packard Company 1992 Compilers for VLIW and superscalar processors have to expose instruction-level parallelism to effectively utilize the hardware. Software pipelining is a scheduling technique to overlap successive iterations of loops, while superblock scheduling extracts ILP from frequently executed traces. This paper describes an effort to employ both software pipelining...

The BOPS ManArray architecture is presented as a coprocessor platform for the embedded processor domain, consisting of scalable design points. As an array processor, a single architecture definition and tool set supports multiple configurations of processing elements (PEs) from low end single PE to large arrays of PEs. The ManArray selectable parallelism architecture mixes control-oriented oper...

The explosive growth in network bandwidth and Internet services such as QoS (quality of service) and SLA (service level agreement) monitoring have created the need for new networking hardware called a Network Processing Unit (NPU). In order to rapidly reconfigure the NPU for frequently varying Internet services and technologies, a high-performance C compiler is urgently needed. Several code gen...

In this project we developed integrative methods for generating high-quality code for embedded and instruction-level parallel processor architectures, including regular architectures such as superscalars and VLIW, as well as irregular architectures, such as clustered VLIW and DSP processors. Even though today’s DSP processors are more compiler friendly than a decade ago or than today’s network ...

Very Long Instruction Word (VLIW) processors are wide-issue statically scheduled processors. Instruction scheduling for these processors is performed by the compiler and is therefore a critical factor for its operation. Some VLIWs are clustered, a design that improves scalability to higher issue widths while improving energy efficiency and frequency. Their design is based on physically partitio...