نتایج جستجو برای: time fpga target
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هدف این تحقیق طراحی و سنتز پردازنده فازی آستانه گیر تصویر دیجیتال با زبان سخت-افزاری vhdl و به منظور پیاده سازی بر روی تراشه fpgaاست. در ابتدای این پژوهش چند الگوریتم آستانه گیری تصویر مورد بررسی قرار گرفت که از بین آنها الگوریتم آستانه گیری مبتنی بر مجموعه های فازی برای پردازنده مورد نظر انتخاب شد. این الگوریتم برای تصاویر با کنتراست پایین به خوبی عمل نمی کرد که برای این منظور یک راهکار ارائه ...
Field programmable gate arrays (FPGAs) are one of the most widespread reconfigurable devices in which various functions can be implemented by storing circuit connection information and logic values into configuration memories. One of the most important issues in the modern FPGA is the reduction of its static leakage power consumption. Flex Power FPGA, which has been proposed to overcome this pr...
the present study is an experimental case study which investigates the impacts, if any, of skopos on syntactic features of the target text. two test groups each consisting of 10 ma students translated a set of sentences selected from advertising texts in the operative and informative mode. the resulting target texts were then statistically analyzed in terms of the number of words, phrases, si...
With the rapid development of China’s economic construction, large-scale infrastructure construction has been carried out in slope area. However, due to poor geological environment, concentrated rainfall, and limited land resources region, a large number toe excavation graded cutting are process engineering construction. The unreasonable method destroys original shape affects stability slope, w...
In this paper, the FPGA routing process is explored to mitigate and take advantage of the effect of delay variability due to process variation. A new method called partial rerouting is proposed in this paper to improve the timing performance based on process variation and reduce the execution time. By only rerouting a small number of critical and near-critical paths, about 6.3% timing improveme...
Two common problems we face in implementing reconngurable systems on currently available FPGA chips are: (1) tting designs which are too big for available hardware resources on a single FPGA chip, (2) lack of synthesis tools for high-level speciications. One solution to address the rst problem is partial reconnguration or run-time recon-guration which requires only loading a portion of the desi...
In this work, the design of a low-cost, field programmable gate array (FPGA)-based digital hardware platform that implements image processing algorithms for real-time distance measurement is presented. Using embedded development kit (EDK) tools from Xilinx, the system is developed on a spartan3 / xc3s400, one of the common and low cost field programmable gate arrays from the Xilinx Spartan fami...
This work describes the identification of designs that benefit from a Dynamic Circuit Specialization (DCS) implementation on FPGAs. In DCS, the circuit is specialized for slowly changing inputs, called parameters. For certain applications or cores, a DCS implementation is faster and smaller than the original implementation. DCS implementations can benefit from the possibility in modern FPGAs to...
( 1. I nstitute of Modern Physics,Chinese Academy of Sciences,LanZhou,730000,China, 2. University of Chinese Academy of Sciences ,Beijing,100039,China) Abstract: A large number of data need to be transmitted in high-speed between Field Programmable Gate Array (FPGA) and Advanced RISC Machines 11 micro-controller (ARM11) when we design a small data acquisition (DAQ) system for nuclear experiment...
Design practices have an enormous impact on an FPGA design’s timing performance, logic utilization, and system reliability. Good design practices also aid in successful design migration between FPGA and ASIC implementations for both prototyping and production. Poor design practices can lead to low performance, high logic or resource utilization, and unstable or unreliable designs associated wit...
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