The advent of ultra deep sub-micron silicon technology (of gate length 0.13 μm and below) has triggered a strong motive to integrate multiple existing functions onto a single chip, called system-on-a-chip or SOC. This is desirable from the consumers’ perspective, as it will, eventually, reduce the overall system cost, size, and power consumption dramatically while enhancing product performance ...

IC and SPI are the most commonly used serial protocols for both inter-chip and intra-chip low/medium bandwidth data-transfers. This paper contrasts and compares physical implementation aspects of the two protocols through a number of recent Xilinx’s FPGA families, showing up which protocol features are responsible of substantial area overhead. This valuable information helps designers to make c...

| Substrate crosstalk modeling and analysis techniques for a reliable SoC oriented mixed signal IC design are outlined. Substrate noise measurements by use of a source follower and a latched comparator clearly indicate that L di=dt and R i e ects on Vdd/Gnd wirings appear in the substrate. An experimental full chip substrate crosstalk veri cation system based on a macroscopic substrate noise mo...

Socware is the name for a new design cluster in Sweden, which intends to unify university, research institutes, and industry towards a common goal, namely System-on-Chip. In this paper, one of the programs within the cluster, the Socware Research & Education Program, is presented. The program aims to organize a new education curriculum for System-on-Chip design. The education is directed to und...

This paper presents the design and implementation of three System on Chip (SoC) cores, which implement the Digital Signal Processing (DSP) functions: Finite Impulse Response (FIR) filter, Infinite Impulse Response (IIR) filter and Fast Fourier Transform (FFT). The FIR filter core is based on the symmetrical realization form, the IIR filter core is based on the Second Order Sections (SOS) archit...

With increasing design complexity System on Chip (SoC) verification is becoming a more and more important and challenging aspect of the overall development process. The Universal Verification Methodology (UVM) is thereby a common solution to this problem; although it still keeps some problems unsolved. In this panel leading experts from industry (both users and vendors) and academy will discuss...

We examine the use of exponential-Golomb codes and subexponential codes can be used for the compression of scan test data in core-based system-on-a-chip (SOC) designs. These codes are well-known in the data compression domain but their application to SOC testing has not been explored before. We show that these codes often provide slighly higher compression than alternative methods that have bee...

This article presents an ultra-low-power parallel computing platform and its system-on-chip (SoC) embodiment, targeting a wide range of emerging near-sensor processing tasks for Internet of Things (IoT) applications. The proposed SoC achieves 193 million operations per second (MOPS) per mW at 162 MOPS (32 bits), improving the first-generation Parallel Ultra-Low-Power (PULP) architecture by 6.4 ...