In this paper, we propose a leakage reduction technique. Because high leakage currents in deep submicron regimes are becoming a major contributor to total power dissipation of CMOS circuits. Sub threshold leakage current plays a very important role in power dissipation. So to reduce the sub threshold leakage current we proposed an adaptive voltage level (AVL) technique. Which optimize the overa...

In order to meet the requirements in real time DSP applications MAC unit is required. The speed of the MAC unit determines the overall performance of the system. MAC unit basically consists of Multiplier, adder and an accumulator unit. In most of the cases floating point adder/subtractor and a multiplier are presented in IEEE-754 format for single precision format. In this research work MAC uni...

Different logic gates like MV, NOT, AOI, NNI etc under QCA nanotechnology are introduced. NNI gate is highly effective regarding space and speed consideration. Any Boolean functions are synthesized by MV and NNI gates or simply NNI gates alone, eliminating inverter (NOT) gate. A new method for realizing adder circuit in binary reversible logic is invented. This procedure synthesizes for a more ...

The IEEE 754 single precision floating point multiplier uses reversible exponent adder to accomplish multiplication operation. The REA is designed and implemented using reversible logic gates like Peres gate and TR gate. Reversible logic is used to reduce the power dissipation compared to classical logic and it can also reduces the information loss so which finds application in different fields...

In this manuscript, an unusual adaptive FIR filter using distributed arithmetic (DA) for area efficient design is implemented. DA is bit-serial computational action and uses parallel look-up table (LUTs) apprise and equivalent implementation of filtering and weight-update operations to appliance high throughput filter rates irrespective of the filter length. The full adder based conditional sig...

ABSTRACT: The field of inexact registering has gotten critical consideration from the exploration group in the previous couple of years, particularly with regards to different flag preparing applications. Picture and video pressure calculations, for example, JPEG, MPEG, et cetera, are especially alluring possibility for inexact registering, since they are tolerant of figuring imprecision becaus...

We present a scalable high-speed divide-by-N frequency divider using only basic digital CMOS circuits. The divider achieves high-speed operation using a novel parallel counter and a pipelined architecture. The parallel counter is based on a state look-ahead component in conjunction with an internal pipeline structure in order to simultaneously trigger all state value updates without a rippling ...

To streamline in vivo biomarker discovery, we developed a suppression subtractive DNA hybridization technique adapted for phage-displayed combinatorial libraries of 12 amino acid peptides (PhiSSH). Physical DNA subtraction is performed in a one-tube-all-reactions format by sequential addition of reagents, producing the enrichment of specific clones of one repertoire. High-complexity phage reper...

This paper presents a dark current suppression technique for a light detector in a variable-temperature system. The light detector architecture comprises a photodiode for sensing the ambient light, a dark current diode for conducting dark current suppression, and a current subtractor that is embedded in the current amplifier with enhanced dark current cancellation. The measured dark current of ...