In this paper, we present a SRAM-PCM hybrid cache design, along with a cache replacement policy, named dead fast block (DFB) to manage the hybrid cache. This design aims to leverage the best features of both SRAM and PCM devices. Compared to a PCM-only cache, the hybrid cache with DFB policy provides superior results on all relevant evaluation metrics, viz. cache lifetime, performance and energ...

This paper describes a multi-functional deep in-memory processor for inference applications. Deep inmemory processing is achieved by embedding pitch-matched low-SNR analog processing into a standard 6T 16KB SRAM array in 65 nm CMOS. Four applications are demonstrated. The prototype achieves up to 5.6X (9.7X estimated for multi-bank scenario) energy savings with negligible (≤1%) accuracy degrada...

A voltage-controlled negative-differential-resistance device using a merged integrated circuit of two n-channel enhancement-mode MOSFETs and a vertical NPN bipolar transistor, called vertical Lambda-bipolar-transistor (VLBT), is presented for memory application. The new VLBT structure has been developed and its characteristics are derived by a simple circuit model and device physics. A novel si...

This paper proposes a realistic memory fault probability model which predicts the probabilities of memory fault classes for a given process technology. Physical defects in the memory array are classified into five functional fault classes, which are stuck-at, stuck-open, transition, coupling, and data retention faults. Finally, the memory fault coverages of the known memory test algorithms are ...

Memories are a core part of most of the electronic systems. Performance in terms of speed and power dissipation is the major areas of concern in today’s memory technology. In this paper SRAM cells based on 6T, 7T, 8T, and 9T configurations are compared on the basis of performance for read and write operations. Studied results show that the power dissipation in 7T SRAM cell is least among other ...

JCHPS Special Issue 1: February 2017 www.jchps.com Page 197 Design of Low Power Content-Addressable Memory using Master–Slave Match Line P. Nithya & S. Tamilselvan Department of Electronics and Communication Engineering, M. Kumarasamy College of Engineering, Karur, Tamil Nadu. *Corresponding author: E-Mail: [email protected] ABSTRACT Content-Addressable Memory is an extension of ordinary m...

A 4096×2160p multiview video encoder chip is implemented on a 3.95mm×2.90mm die with 90nm CMOS technology. A view-parallel macroblock-interleaved scheduling with 8stage macroblock pipelined architecture achieves 212Mpixels/s throughput, which is 3.4× to 7.7× better than the state-of-the-art encoder chips. In addition, 94% on-chip SRAM area and 79% external system memory bandwidth are saved.

A 256 144-bit TCAM is designed in 0.18m CMOS. The proposed TCAM cell uses 4T static storage for increased density. The proposed match-line (ML) sense scheme reduces power consumption by minimizing switching activity of search-lines and limiting voltage swing of MLs. The scheme achieves a match-time of 3 ns and operates at a minimum supply voltage of 1.2 V.

Based on the observation that dynamic occurrence of zeros in the cache access stream and cacheresident memory values of ordinary programs exhibit a strong bias towards zero, this paper presents a novel CMOS five-transistor SRAM cell (5T SRAM cell) for very high density and low power cache applications. This cell retains its data with leakage current and positive feedback without refresh cycle. ...

This paper deals with design opportunities of Static Random Access Memory (SRAM) for low power consumption. Initially three major leakage current components are reviewed and then for a 6T SRAM cell, some of the leakage current reduction techniques are discussed. Finally double finger latch is analyzed and compared with single finger latch which shows reduction in sub threshold leakage current.