Sub-threshold is a new paradigm in the digital VLSI design today. In Sub-threshold region, transistors are operated in sub-threshold voltage. This paper examine the Carry Look Ahead (CLA) Adder with dual mode logic (DML)principle, in which gates are operated in sub-threshold regime and comparison of results with Conventional basic Carry look ahead adder . The number of gates in CLA is 5 includi...

Hardware designers are constantly looking for ways to squeeze waste out of architectures to achieve better power efficiency. Cache resizing is a technique that can remove wasteful power consumption in caches. The idea is to determine the minimum cache a program needs to run at near-peak performance, and then reconfigure the cache to implement this efficient capacity. While there has been signif...

An adder is one of the most integral component of a digital system like a digital signal processor or a microprocessor. Being an extremely computationally intensive part of a system, the optimization for speed and power consumption of the adder is of prime importance. In this paper we have designed a 1 bit full adder cell based on dynamic TSPC logic to achieve high speed operation. A high thres...

Power modeling techniques have traditionally neglected the main part of the energy consumed in the internal nodes of static CMOS gates: the power dissipated by input transitions that do not produce output switching. In this work, we present an experimental set-up that shows that this power component may contribute up to 59% of the total power consumption of a gate in modern technologies. This f...

Load modeling is widely used in power system studies. Two types of modeling, namely, static and dynamic, are employed. The current industrial practice is the static modeling. Static modelss are algebraic equations of active and reactive power changes in terms of voltage and frequency deviations. In this paper, a component based on static modeling is employed in which the aggregate model is deri...

A Delay (D) flip-flop is an edge triggering device. A high speed, low power consumption, positive edge triggered conventional Delay (D) flip-flop can be designed for increasing the speed of counter in Phase locked loop, using 32nm CMOS technology. The conventional D flip-flop has higher operating frequencies but it features static power dissipation. The designed counter can be used in the divid...

As a method for greatly reducing power dissipation in logic networks, we propose some logic organization techniques for logic networks. By such techniques, their power dissipation is to be minimized under certain input conditions, or the average power dissipation in the whole network should be minimized. A logic network in which these problems are taken into account will be called a power minim...

This paper addresses the issues of power dissipation and propagation delay in CMOS buffers driving large capacitive loads and proposes a CMOS buffer design for improving power dissipation at optimized propagation delay. The reduction in power dissipation is achieved by minimising short circuit power and subthreshold leakage power which is predominant when

Low power consuming devices are playing a dominant role in the present day VLSI design technology. If the power consumption is less, then the amount of power dissipation is also less. The power dissipation of a device can be reduced by using different low power techniques. In the present paper the performance of 4x1 multiplexer in different low power techniques was analyzed and its power dissip...

-In recent years, low power circuit design has been an important issue in System on Chip (SoC) and VLSI design areas. Adiabatic logics, which dissipate less power than static CMOS logic, have been introduced as a promising new approach in low power circuit design. Adiabatic circuits are those circuits which work on the principle of adiabatic charging and discharging and which recycle the energy...