This paper presents a CMOS four-transistor SRAM cell for very high density and low power embedded SRAM applications as well as for stand-alone SRAM applications. The new cell size is 35.45% smaller than a conventional sixtransistor cell using same design rules. Also proposed cell uses two word-lines and one pair bit-line. Read operation perform from one side of cell, and write operation perform...

A highly stable 8T SRAM cell is presented to improve the Static Noise Margin (SNM). The proposed 8T SRAM cell uses a single-bit line structure to perform read and write operation. The design enhances the write ability by breaking-up the feedback loop of the inverter pair. It also improves the read stability by eliminating the effects from the bit-line. The simulations show that the proposed 8T ...

In this study, we propose a lightweight and low-latency advanced encryption standard (AES) accelerator. Instead of being connected to the bus through its own slave wrapper, proposed AES accelerator is located within wrapper static random-access memory (SRAM) directly attached SRAM. Hence, can access data in SRAM share space for storing expanded keys, resulting no time transferring input output ...

Thangamani.V Kalaignar Karunanidhi Institute of Technology, Chennai Anna University, Kannampalayam(PO),Coimbatore-641402,TamilNadu,India. Contact No.:8675802322, E-mail: [email protected] Abstract The computer memory system has both volatile and non volatile memory. The Volatile memories such as SRAM and DRAM used as a main memory and non volatile memory like flash memory. But in recent days...

In Present scenario battery-powered hand-held multimedia systems become popular. The power consumption in these devices is a major concern these days for its long operational life. Although various techniques to reduce the power dissipation has been developed. The most adopted method is to lower the supply voltage. But lowering the Vdd reduces the gate current much more rapidly than the sub-thr...

Problem statement: As technology scales down, the integration density of transistors increases and most of the power is dissipated as leakage. Leakage power reduction is achieved in Static Random Access Memory (SRAM) cells by increasing the source voltage (source biasing) of the SRAM array. Another promising issue in nanoscaled devices is the process parameter variations. Due to these variation...

In this paper we propose a novel design of a low power static random access memory (SRAM) cell for high-speed operations. The model adopts the voltage mode method for reducing the voltage swing during the write operation switching activity. Dynamic power dissipation increases when the operating frequency of the SRAM cell increases. In the proposed design we use two voltage sources connected wit...

Carbon nanotube field-effect transistor (CNTFET) refers to a field-effect transistor that utilizes a single carbon nanotube or an array of carbon nanotubes as the channel material instead of bulk silicon in the traditional MOSFET structure. Since it was first demonstrated in 1998, there have been tremendous developments in CNTFETs, which promise for an alternative material to replace silicon in...

Scaling of SRAM cell beyond 65-nm poses a serious threat to the stability of the cell and is a cause of major concern for the upcoming technologies. Due to random dopant fluctuation (RDF) and other process parameter variations, the cell turns out to be unstable. In this paper, an 8T (8Transistor) SRAM cell is proposed which offers enhanced data stability during read operation. While reading, th...