This work presents a study of the use of a transistor with a different configuration in the channel region, named GradedChannel (GC), for analog application in current mirror circuits with different architectures: Common-source, Cascode and Wilson. A comparison will be done between current mirrors implemented with standard (uniformly doped) SOI and GC SOI nMOSFETs by using simulation and experi...

In this paper we describe usage of FreeBSD operating system for IPv6 Multicast routing platform in SOI-Asia Project. SOI-Asia project is platform to deliver realtime lecture via UniDirectional Link of satellite to several countries in Asia. Because of limited bandwidth in satellite, we use IPv6 multicast to deliver material of lecture and realtime video and audio lecture. We also describe human...

Interest in SOI technology has been increased due to recent progress in modeling parasitic effects needed for analog IC design. In this paper a brief overview of the SOI technology is done. A user compiled model built for ADS is then described before the analysis of 2 RF designs: a wideband Low Noise Amplifier (300MHz-900MHz with more than 10dB gain and 5dBm IIP3) and an antenna switch (with 0....

We present an numerical investigation of a planar waveguide surface plasmon resonance (SPR) sensor in silicon-oninsulator (SOI) for detecting a change in the imaginary part of the refractive index. By adding a thin adsorbed layer between the metal-analyte boundary it is found that an enhanced sensitivity of the sensor is obtained, suggesting the possibility of realizing a highly integrated and ...

This article presents the comparison of SingleGate SOI and Multi-Gate SOI MOSFETs. In the first part we have presented two main fundamental problems of the “ultimate” (sub-10-nm) MOSFET scaling of Single-Gate geometry: the exponential growth of power consumption and sensitivity to fabrication uncertainties. These factors have played the decisive role in for eventual transfer of the CMOS industr...

1. Abstract We propose 7T/14T FD-SOI SRAM with a substrate bias control mechanism. The 14T configuration suppresses intra-die variation in a bit cell. The substrate bias control circuits detect a threshold voltage and automatically change it with the substrate bias. Thereby, the inter-die variation is suppressed. By combining these two schemes, we confirmed that a 576-kb SRAM test chip in a 0.1...

In this paper, the reliability issues of the lateral insulator gate bipolar transistor based on SOI substrate (SOI-LIGBT), including the anode punch-through, the terminal early breakdown, the hot-carrier degradation and the latch-up failure, have been experimentally investigated and improved. The measurement results and the T-CAD simulations demonstrate that the proposed device owns higher reli...

Trends in modeling and measurements of the Soft Error Rate (SER) critical charge (Qcrit) for recent generation CMOS SOI devices are reviewed. Modeling and measurements as a function of voltage on 65, 45, 32 and 22 nm planar, SOI devices will be presented. The modeling techniques used will be reviewed and, where possible, compared to experimental measurements. Finally modeling of new device stru...

Application of the VT-control method is studied in ultrathin double-gate (DG) SOI inverter, as the simplest building block of SOI logic circuits. Two control voltages, VCN and VCP, are applied to the back-gates of the n-type and p-type transistors, respectively, to reduce the leakage current when the inverter is in the idle mode. Simulations with DESSIS disclose that both control voltages may b...

MOS Technology on massive substrate played a critical task during micro-electronic evolution. The regular reduction of transistors sizes leads today to nanometric devices. With this reduction, some parasitic physical effects, previously with no importance, became mostly amplified, leading to the end of MOSFETs technology on massive substrate. SOI technology gives a good alternative to that mini...