This paper proposes a new energy management framework for an IP over WDM network. A key constraint of our architecture is to maintain the logical IP topology while saving energy by infrastructure sleeping and virtual router migration. Since the traffic in a network typically has a regular diurnal pattern based on people’s activities, some virtual routers can be moved to a smaller set of physica...

This thesis describes the implementation of a router chip for a network of processors. The router features the simultaneous bidirection pad drivers and a diagnostic port with a JTAG interface. The design process results in some useful experience for the development of a complex VLSI system in an academic research environment. The router chip is designed for a 3.3v 0.8pm 3 metal layers CMOS proc...

This work presents the architecture and ASIC implementation of Hermes-A, an asynchronous network on chip router. Hermes-A is coupled to a network interface that enables communication between router and synchronous processing elements. The ASIC implementation of the router employed standard CAD tools and a specific library of components. Area and timing characteristics for 180nm technology attes...

The system (see Figure 2) uses a neural network, called a “router”, to analyze each window of the input before it is processed by a “detector” network. If the window contains a face, the router returns the angle of the face. The window can then be “derotated” to make the face upright. The derotated window is then passed to the detection network, which decides whether a face is present. If a non...

Dynamic Circuit Specialization (DCS) is a new FPGA CAD tool flow that uses Run-Time Reconfiguration to automatically specialize the FPGA configuration for a whole range of specific data values. DCS implementations are a factor 5 faster and need a factor 8 less luts compared to conventional implementations. We propose a novel routing algorithm for reconfigurable routing, called the Connection ro...

The WARRP router implements progressive deadlock recovery-based true-fully-adaptive routing in an efficient architecture designed to maximize flexibility as well as speed. The WARRP II version addresses the I/O pin-out problem by integrating dense high-bandwidth optoelectronic transceivers onto the router chip capable of providing over 300 GBytes/sec per square centimeter [7]. To our knowledge,...

This document describes an optional extension to Router Advertisement messages for communicating default router preferences and morespecific routes from routers to hosts. This improves the ability of hosts to pick an appropriate router, especially when the host is multi-homed and the routers are on different links. The preference values and specific routes advertised to hosts require administra...

Technology makes it easier for us to communicate over a distance. However, there are still many remote areas that find difficult communicate. This is due the fact communication infrastructure in some expensive build while profit will be low. paper proposes combine voice internet protocol (VoIP) mesh network implemented on openWRT router. The routers performing functions. We set up VoIP server r...

Advances in semiconductor technology have let microprocessors integrate more than a 100 million transistors on a single chip. The Alpha 21364 microprocessor uses 152 million transistors to integrate an Alpha 21264 processor core, a 1.75-Mbyte second-level cache, cache coherence hardware, two memory controllers, and a multiprocessor router on a single die, as Figure 1a shows. In the 0.18-micron ...

A distributed multistage software router (MSSR) is composed by several interconnected software routers running on personal computers (PCs). The MSSR architecture overcomes scalability and performance issues of single software router by providing parallel forwarding paths. Like many networking devices, a MSSR must be sized for peak traffic load, which implies energy inefficiency at low loads. Th...