This paper presents a structure of TLB (translation lookaside buffer) for low power consumption but high performance. The propsed TLB is constructed as a combination of one block buffer and two-way banked TLBs. The processor can access the block buffer or one of two banked TLBs selectively. This feature is quite different from that used in the traditional block buffering technique. Simulation r...

In this paper a novel low power double edge pulse triggered flip flop (FF) design is present. First, the pulse generation control logic by using the NAND function and is removed from the critical path to facilitate a faster discharge operation. A simple two transistor NAND gate design is used to reduce the circuit complexity. Second, a double edge conditional discharging flip flop is used to re...

The Markov random field (MRF) theory has been accepted as a highly effective framework for designing noise-tolerant nanometer digital VLSI circuits. In MRF-based design, proper feedback lines are used to control noise and keep the circuits in their valid states. However, this methodology has encountered two major problems that have limited the application of highly noise immune MRF-based circui...

Reversible logic has attracted substantial interest due to its low power consumption which is the main concern of low power VLSI circuit design. In this paper, a novel 4x4 reversible gate called inventive gate has been introduced and using this gate 1-bit, 2-bit, 8-bit, 32-bit and n-bit group-based reversible comparator have been constructed with low value of reversible parameters. The MOS tran...

ABSTRACT This paper proposes a sleep transistor based minimum size inverter in BSIM4.3.0, 50nm CMOS technology with supply voltage of 1V, power dissipation of 46.28nW at 0.502V and maximum drain current of 70nA. The operating frequency is kept at 1GHz, and found that it can be used up to 10GHz successfully. The reduction in power dissipation is 98.88% and operating frequency is almost 2 times t...

This paper proposes a Dual Pai-Sigma Segment Matchline scheme to reduce the search (compare) power of a Ternary Content Addressable Memory (TCAM). The proposed Matchline does not incur the issues of short circuit current and charge sharing, which typically exist in the hybrid NAND-NOR Matchline. The proposed scheme is designed using 6T NAND&NOR TCAM cells and 4T NAND & NOR TCAM cells and their ...

Most important challenge in modern VLSI design along with area and speed is the power consumption. Flip flop is the basic element in digital system which plays very important role. In this paper, a low power pulse triggered flip flop with feed through technique is proposed. The proposed design introduces a series pass transistor which helps in reducing discharging path. By performing post layou...

Current comparator is a fundamental component of current-mode analog integrated circuits. A novel high-performance continuous-time CMOS current comparator is proposed in this paper, which comprises one CMOS complementary amplifier, two resistive-load amplifiers and two CMOS inverters. A MOS resistor is used as the CMOS complementary amplifier’s negative feedback. Because the voltage swings of t...

The Energy-Delay product or ED product was proposed as a metric to gauge design effectiveness. This metric is widely used in the area of low-power architecture research, however it is also often improperly used when reporting a new architecture design that addresses energy-performance effectiveness. In this paper, we discuss two common fallacies from the literature: (1) the way the ED product i...

The performance of a semiconducting carbon nanotube (CNT) is assessed and tabulated for parameters against those of a metal-oxide-semiconductor field-effect transistor (MOSFET). Both CNT and MOSFET models considered agree well with the trends in the available experimental data. The results obtained show that nanotubes can significantly reduce the drain-induced barrier lowering effect and subthr...