This paper presents analyses and experimental results on the jitter transfer of delay-locked loops (DLLs). Through a -domain model, we show that in a widely used DLL configuration, jitter peaking always exists and high-frequency jitter does not get attenuated as previous analyses suggest. This is true even in a firstorder DLL and an overdamped second-order DLL. The amount of jitter peaking is s...

This paper describes a low-voltage, low-jitter clock synthesizer and a temperaturecompensated tunable oscillator. Both of these circuits employ a self-correcting Delay-Locked Loop (DLL) which solves the problem of false locking associated with conventional DLLs. This DLL does not require the delay control voltage to be set on power-up, it can recover from missing reference clock pulses and beca...

PLL Basics A phase-locked loop is a feedback system combining a voltagecontrolled oscillator and a phase comparator so connected that the oscillator frequency (or phase) accurately tracks that of an applied frequencyor phase-modulated signal. Phase-locked loops can be used, for example, to generate stable output frequency signals from a fixed low-frequency signal. The first phase-locked loops w...

--The All-Digital Phase-Locked Loop (ADPLL) is digital electronic circuit that are used in modern electronic communication systems like frequency synthesizer, modulator/demodulator etc. This paper presents a review of various ADPLL techniques. The range of input frequency of ADPLL is 40 to 98 MHz; the output frequency may be up to 2.92 to 4 GHz range. The components of ADPLL such as phase detec...

Loop closing is a vital component for mobile robot navigation without a priori information of the environment, since the mobile robot has to explore, build and at the same time maintain a globally consistent map. Moreover, it allows the mobile robot to recover from positional drifts due to errors associated with sensor measurements once loop closing is performed. In this paper, an active loop c...

This paper is a review of methods and techniques used for precise measurement of time intervals (TIs) or precise conversion of TIs to digital data. The following methods are described: the counter method and averaging, time stretching, time-to-amplitude conversion followed by analogue-to-digital conversion, the Vernier method, conversion utilizing tapped delay lines, and interpolation methods. ...

There is several application of phase locked loop in the field of communication. It depends on the mixed signal operation. It is capable of fast locking capability. present work based on redesign of the PLL system using 90nm technology process at frequency 1 GHz and the lock time is 179.5 ns and transient analysis of the PLL is simulate between 1ns to 1000ns.it consumes the 179.5 mW power at 1....

In this paper a new architecture for delay locked loops will be presented.  One of problems in phase-frequency detectors (PFD) is static phase offset or reset path delay. The proposed structure decreases the jitter resulted from PFD by switching two PFDs. In this new architecture, a conventional PFD is used before locking of DLL to decrease the amount of phase difference between input and outpu...