In this article, a C-testable design for detecting transition faults in the polynomial basis (PB) bit parallel (BP) multiplier circuits over GF(2) is discussed. For 100 percent transition fault coverage, the proposed technique requires only 10 vectors, irrespective of multiplier size, at the cost of 6 percent extra hardware. The proposed constant test vectors which are sufficient to detect both...

A parallel structure for a CMOS four-quadrant analog multiplier is proposed and analyzed. By applying differential input signals to a set of combiners, the multiplication function can be implemented. Based on the proposed structure, a low-voltage high-performance CMOS four-quadrant analog multiplier is designed and fabricated by 0.8m N-well doublepoly-double-metal CMOS technology. Experimental ...

This paper presents a throughput/area-efficient hardware accelerator architecture for elliptic curve point multiplication (ECPM) computation over GF(2233). The throughput of the proposed design is optimized by reducing total clock cycles using bit-parallel Karatsuba modular multiplier. We employ two techniques to minimize resources: (i) consolidated arithmetic unit where we combine single adder...

Target detection for hyperspectral images (HSIs) is one of the significant techniques in remote sensing data processing. Targets generally comprise various object categories with complex features and varying sizes. often used application scenarios which accurately efficiently acquiring results can be challenging. The development advanced target approaches becoming increasingly necessary both mi...

Computationally intensive inference tasks of deep neural networks have brought about a revolution in accelerator architecture, aiming to reduce power consumption as well latency. The key figure-of-merit hardware accelerators is the number multiply-and-accumulation operations per watt (MACs/W); state-of- the-art MACs/W, so far, has been several hundreds Giga-MACs/W. We propose Tera- MACS/W (TMA)...

The paper presents a new multiplier enabling achievement of an arbitrary accuracy. It follows the same idea of number representation as the Mitchell’s algorithm, but does not use logarithm approximation. The proposed iterative algorithm is simple and efficient and its error percentage is as small as required. As its hardware solution involves adders and shifters, it is not gate and power consum...

This paper presents a new concept for a parallel neurocom-puter architecture which is based on a conngurable neuroprocessor design. The neuroprocessor adapts its internal parallelism dynamically to the required data precision for achieving an optimal utilization of the available hardware resources. This is realized by encoding a variable number of p diierent data elements in one very long data ...