A routing scheme is one of the fundamental mechanisms in packet switched networks. Its importance and effect on the performance of the network is accordingly cardinal. In this report we discuss the possibility of using adaptive routing in NoCs. We examine several adaptation techniques and present their advantages and drawbacks. 1 NoC: Switching, Routing and

The concept of Network on Chip (NoC) is a promising solution for high performance computing systems. It is implemented by placing the different processing modules on a single chip allowing efficient interaction through an interconnection network. This paper presents a comparative performance study of mesh and torus commonly used interconnection networks. To compare the performance, the paramete...

Rex Lee [email protected] Abstract An improved version of stream arbitration based on multiband RF interconnect (MRFI) is proposed. Thanks to the simultaneous multiple channel transmitting/receiving feature of MRFI, dynamic bandwidth allocation is achieved in the proposed arbitration algorithm. With dynamic bandwidth allocation, MRFI based arbitration can guarantee 100% channel bandwidth u...

MOTIVATION Many biological networks, including transcriptional regulation, metabolism, and the absorbance spectra of metabolite mixtures, can be represented in a bipartite fashion. Key to understanding these bipartite networks are the network architecture and governing source signals. Such information is often implicitly imbedded in the data. Here we develop a technique, network component mappi...

On-chip implementation of multiprocessor systems requires the planarization of the interconnect network onto the silicon floorplan. Manual floorplanning approaches will become increasingly more difficult and ineffective as multiprocessor complexity increases. Compared with traditional ASIC architectures, multiprocessors have homogeneous processing elements and regular network topologies. Theref...

Creating Network on Chip is done here, we present a new network-on-chip (NoC) that handles accurate localizations of the faulty parts of the NoC. The implemented design NoC is based on new error detection mechanisms suitable for dynamic NoCs, where the number and position of processor elements or faulty blocks vary during runtime. Indeed, We designed a online detection of data packet and adapti...

We present a new architecture level unified reliability evaluation methodology for chip multiprocessors (CMPs). The proposed reliability estimation (REST) is based on a Monte Carlo algorithm. What distinguishes REST from the previous work is that both the computational and communication components are considered in a unified manner to compute the reliability of the CMP. We utilize REST tool to ...

This paper presents a framework for high-level exploration and RTL design of an optimized Network-on-Chip (NoC) architecture for 3D chips. The RTL is derived from the high-level exploration methodology in a semi-automated way. FPGA implementation figures are given for various implementation parameters of the Network Interface Element, demonstrating the performance/area trade-off of 3D NoC archi...

Future wireless communications networks require flexible modem architectures with high performance. Efficient utilization of application specific flexibility is key to fulfill these requirements. For high throughput a single processor can not provide the necessary computational power. Hence multiprocessor architectures become necessary. This paper presents a multi-processor platform based on a ...